Add YOSYS to the implicitly defined verilog macros in verific
authorClaire Xenia Wolf <claire@clairexen.net>
Mon, 13 Dec 2021 17:20:08 +0000 (18:20 +0100)
committerClaire Xenia Wolf <claire@clairexen.net>
Mon, 13 Dec 2021 17:20:08 +0000 (18:20 +0100)
commit313340aed5e7d21a52d67c0a3c2bbc1623e87315
tree8d028249a254fd8ef4190c916b673db9362c19a4
parent19a38222e78b0b29b9adbf2c9fcd2d1c701c7e17
Add YOSYS to the implicitly defined verilog macros in verific

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
frontends/verific/verific.cc