Merge pull request #2006 from jersey99/signed-in-rtlil-wire
authorwhitequark <whitequark@whitequark.org>
Thu, 4 Jun 2020 11:23:06 +0000 (11:23 +0000)
committerGitHub <noreply@github.com>
Thu, 4 Jun 2020 11:23:06 +0000 (11:23 +0000)
commit3bffd09d6423b70ca154527c363985ff048f807d
tree5d38c0618e478722d8dcd0fb681ef443869f0b8c
parent44f1e651558c5063b6e0c4496d916abc23329751
parentadb483ddfd3163a4efa08e09a35dd926377aa71d
Merge pull request #2006 from jersey99/signed-in-rtlil-wire

Preserve 'signed'-ness of a verilog wire through RTLIL
frontends/ast/genrtlil.cc
frontends/ilang/ilang_parser.y
kernel/rtlil.cc
kernel/rtlil.h