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(parent: 07a657f) | patch
verilog backend: Emit a `wire` for ports as well.
authorMarcelina Kościelnicka <mwk@0x04.net>
Sun, 30 Jan 2022 19:48:50 +0000 (20:48 +0100)
committerMarcelina Kościelnicka <mwk@0x04.net>
Mon, 31 Jan 2022 00:08:41 +0000 (01:08 +0100)
commit56e7791760ce67cb1831691460b50bf73a4f5117
treeadd3d8b2488630378d8152b4c305ff99bd27b75ftree
parent07a657fb0ca08012af3de410520458af255b1097commit | diff
verilog backend: Emit a `wire` for ports as well.

Fixes #3177.
backends/verilog/verilog_backend.cc diff | blob | history