Merge pull request #3297 from jix/sva_nested_clk_else
authorJannis Harder <me@jix.one>
Mon, 9 May 2022 14:07:39 +0000 (16:07 +0200)
committerGitHub <noreply@github.com>
Mon, 9 May 2022 14:07:39 +0000 (16:07 +0200)
commit5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd
treefa7a31d02a6de07779a4f7b7934fb662c5efc06d
parentd562bfd165b3c107abf717d2661c44aa2b7740fb
parent96f64f4788ca64adde55421a6abadefd182d9a1a
Merge pull request #3297 from jix/sva_nested_clk_else

verific: Fix conditions of SVAs with explicit clocks within procedures