rename JTAG port in adder test experiments10_verilog (success compile)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 12 Apr 2021 10:54:57 +0000 (10:54 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 12 Apr 2021 10:54:57 +0000 (10:54 +0000)
commit5da6eed52e9eeb94001f98d18469e1692125ce9f
tree035442449ae7484e2c7317ef18cf39a945c6bbab
parent9610fba9110f85e497019f915f5f7e4caab1380d
rename JTAG port in adder test experiments10_verilog (success compile)
experiments10/coriolis2/ioring.py
experiments10_verilog/add.py
experiments10_verilog/coriolis2/settings.py
experiments10_verilog/doDesign.py