Merge pull request #3108 from YosysHQ/claire/verificdefs
authorClaire Xen <claire@clairexen.net>
Mon, 13 Dec 2021 21:03:29 +0000 (22:03 +0100)
committerGitHub <noreply@github.com>
Mon, 13 Dec 2021 21:03:29 +0000 (22:03 +0100)
commit5e5c8a54ce56efcc0f3144736d4cf7fd2314aa83
tree8d028249a254fd8ef4190c916b673db9362c19a4
parent19a38222e78b0b29b9adbf2c9fcd2d1c701c7e17
parent313340aed5e7d21a52d67c0a3c2bbc1623e87315
Merge pull request #3108 from YosysHQ/claire/verificdefs

Add YOSYS to the implicitly defined verilog macros in verific