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(parent: 4ee9c53) | patch
Add verilog submodule from CPU cores to manifest
authorArnaud Durand <arnaud.durand@unifr.ch>
Wed, 3 Jul 2019 22:58:26 +0000 (00:58 +0200)
committerGitHub <noreply@github.com>
Wed, 3 Jul 2019 22:58:26 +0000 (00:58 +0200)
commit68eeba918186f5bd3d3f4e0552b286f7db08d5a3
treeb3bae92bb479a9df7470af0633179a63bb18f971tree
parent4ee9c53f185ac6dd9c4aa69a7547e9bc037acc25commit | diff
Add verilog submodule from CPU cores to manifest
MANIFEST.in diff | blob | history