opcodes: microblaze: Add new bit-field instructions
authorNeal Frager <neal.frager@amd.com>
Thu, 5 Oct 2023 12:51:03 +0000 (13:51 +0100)
committerMichael J. Eager <eager@eagercon.com>
Fri, 6 Oct 2023 17:53:45 +0000 (10:53 -0700)
commit6bbf249557ba17cfebe01c67370df4da9e6a56f9
treeb1242471838ab0e7131aec8879013c258ef8a992
parent9a896be33224654760c46d3698218241d0a1f354
opcodes: microblaze: Add new bit-field instructions

This patches adds new bsefi and bsifi instructions.
BSEFI- The instruction shall extract a bit field from a
register and place it right-adjusted in the destination register.
The other bits in the destination register shall be set to zero.
BSIFI- The instruction shall insert a right-adjusted bit field
from a register at another position in the destination register.
The rest of the bits in the destination register shall be unchanged.

Further documentation of these instructions can be found here:
https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref

This patch has been tested for years of AMD Xilinx Yocto
releases as part of the following patch set:

https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils

Signed-off-by: nagaraju <nagaraju.mekala@amd.com>
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
bfd/bfd-in2.h
bfd/elf32-microblaze.c
bfd/libbfd.h
bfd/reloc.c
binutils/readelf.c
gas/config/tc-microblaze.c
include/elf/microblaze.h
opcodes/microblaze-dis.c
opcodes/microblaze-opc.h
opcodes/microblaze-opcm.h