verilog: attributes before task enable (but 13 s/r conflicts)
authorEddie Hung <eddie@fpgeh.com>
Thu, 14 May 2020 23:10:11 +0000 (16:10 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 14 May 2020 23:10:11 +0000 (16:10 -0700)
commit7101ef550ba4b215d41fc82e52e3aa714afcbdbe
tree8b944106d4f9f69929fddd053f9535f1efe7ec2e
parente7fd8912f041462bf044b6c93aa4b4db786d01c7
verilog: attributes before task enable (but 13 s/r conflicts)
frontends/verilog/verilog_parser.y