projects / nmigen.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 4887771) | patch
test.compat: reenable tests converting to Verilog.
authorwhitequark <whitequark@whitequark.org>
Sat, 26 Jan 2019 15:29:09 +0000 (15:29 +0000)
committerwhitequark <whitequark@whitequark.org>
Sat, 26 Jan 2019 15:29:09 +0000 (15:29 +0000)
commit7890c0adc8e55c7ca5f48abe802c98137c71c596
treedf0756986df99ba5dcf31c307b40792679cc74cctree
parent4887771e4a67dcd766736ec8c00b04ffb5d5ca92commit | diff
test.compat: reenable tests converting to Verilog.
nmigen/compat/fhdl/verilog.py diff | blob | history
nmigen/test/compat/support.py diff | blob | history