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(parent: 4d32580) | patch
ClockDomain.{rst→reset}, for consistency with ResetInserter.
authorwhitequark <whitequark@whitequark.org>
Wed, 12 Dec 2018 09:49:02 +0000 (09:49 +0000)
committerwhitequark <whitequark@whitequark.org>
Wed, 12 Dec 2018 09:49:02 +0000 (09:49 +0000)
commit851ed06769c5f4946287dac80e49d55180a7f41b
treec5fe13dd20cc10aaecf72a543bda4959c39b6bb1tree
parent4d3258013dbb16619bd9a822461953a769e7b72acommit | diff
ClockDomain.{rst→reset}, for consistency with ResetInserter.

nmigen.compat.ClockDomain would alias this, for Migen compatibility.
examples/arst.py diff | blob | history
nmigen/back/rtlil.py diff | blob | history
nmigen/fhdl/cd.py diff | blob | history
nmigen/fhdl/ir.py diff | blob | history