[libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
authorwhygee <whygee@f-cpu.org>
Fri, 8 May 2020 15:27:06 +0000 (17:27 +0200)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 8 May 2020 15:27:08 +0000 (16:27 +0100)
commit9d411c28ca158830b8a0a38eec63e3887c896fef
tree977ea7618c96fc2a398e5e8de89dd5bae9d6f957
parentb33da8f17d79177143996d1bd6c217180e209adb
[libre-riscv-dev] Debug port (was Re:  minimum viable ASIC)
a7/b20094b44be4c1d6bd7f803450990809288fdf [new file with mode: 0644]