RISC-V: Add support for the Zvkg ISA extension
authorChristoph Müllner <christoph.muellner@vrull.eu>
Fri, 30 Jun 2023 20:43:46 +0000 (22:43 +0200)
committerJeff Law <jlaw@ventanamicro>
Sat, 1 Jul 2023 13:28:40 +0000 (07:28 -0600)
commit9d469329d229da8e2a6d7b70a2be3988aa45a277
tree1e6e7cbaf08250da688d92b21f32a21f70c614ae
parentc0a98a853d5ccde35dca20ad5d7cea0a70e16d56
RISC-V: Add support for the Zvkg ISA extension

Zvkg is part of the vector crypto extensions.

This extension adds the following instructions:
- vghsh.vv
- vgmul.vv

bfd/ChangeLog:

* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvkg.
(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

* testsuite/gas/riscv/zvkg.d: New test.
* testsuite/gas/riscv/zvkg.s: New test.

include/ChangeLog:

* opcode/riscv-opc.h (MATCH_VGHSH_VV): New.
(MASK_VGHSH_VV): New.
(MATCH_VGMUL_VV): New.
(MASK_VGMUL_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvkg.

opcodes/ChangeLog:

* riscv-opc.c: Add Zvkg instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
bfd/elfxx-riscv.c
gas/testsuite/gas/riscv/zvkg.d [new file with mode: 0644]
gas/testsuite/gas/riscv/zvkg.s [new file with mode: 0644]
include/opcode/riscv-opc.h
include/opcode/riscv.h
opcodes/riscv-opc.c