hdl.mem: tie rdport.en high for asynchronous or transparent ports.
authorwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 04:22:16 +0000 (04:22 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 04:22:16 +0000 (04:22 +0000)
commita061bfaa6c94752a3fd062b2a6a26a783018aad8
tree09a4b1c48ace59dd3a2a7143e397e0d278c8737c
parent8d58cbf230d1bb63d837bcbf6b0fe7029f8dd126
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
examples/mem.py
nmigen/back/verilog.py
nmigen/hdl/mem.py