experiment with nmigen verilog generation
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Apr 2021 12:37:38 +0000 (12:37 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Apr 2021 12:37:38 +0000 (12:37 +0000)
commitacf9a74a04e8866aae0a738b02343ae772171b5e
tree48a34adb8b19f9590da130d250dbb2dcb55217fe
parent4e8f0957917307f5bba7466c336d2eade537811a
experiment with nmigen verilog generation
experiments10_verilog/Makefile [new file with mode: 0755]
experiments10_verilog/add.py [new file with mode: 0644]
experiments10_verilog/coriolis2/__init__.py [new file with mode: 0644]
experiments10_verilog/coriolis2/ioring.py [new file with mode: 0644]
experiments10_verilog/coriolis2/katana.py [new file with mode: 0644]
experiments10_verilog/coriolis2/settings.py [new file with mode: 0644]
experiments10_verilog/doDesign.py [new file with mode: 0644]
experiments10_verilog/mksym.sh [new symlink]
experiments10_verilog/netlists.txt [new file with mode: 0644]