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(parent: 4f08af6) | patch
radv: align pipeline cache entry and header sizes
authorRhys Perry <pendingchaos02@gmail.com>
Thu, 6 Aug 2020 13:39:04 +0000 (14:39 +0100)
committerMarge Bot <eric+marge@anholt.net>
Thu, 20 Aug 2020 10:52:19 +0000 (10:52 +0000)
commitb50ae770144ef6622591c7cc23aa96e45933cf37
tree8122104d25ab644d9539241ad00ded57040fae5btree
parent4f08af6766c23295922a08a95d0183820f7bc702commit | diff
radv: align pipeline cache entry and header sizes

Fixes UBSan error:
../src/amd/vulkan/radv_pipeline_cache.c:603:42: runtime error: member access within misaligned address 0x00000152ebcc for type 'struct cache_entry', which requires 8 byte alignment

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6206>
src/amd/vulkan/radv_pipeline_cache.c diff | blob | history