rename InternalOp to MicrOp
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 12 Jul 2020 22:01:50 +0000 (23:01 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 12 Jul 2020 22:01:50 +0000 (23:01 +0100)
commitb92b8d7f87b8700d879413579d996690d0fda17f
tree52dd75cfda5d181255d5e486d515b62901abf3b8
parent6e78d390faf2b5a48a4f4b1cbf7ac0c859f6fc23
rename InternalOp to MicrOp
67 files changed:
src/soc/decoder/decode2execute1.py
src/soc/decoder/formal/proof_decoder.py
src/soc/decoder/formal/proof_decoder2.py
src/soc/decoder/isa/caller.py
src/soc/decoder/power_decoder.py
src/soc/decoder/power_decoder2.py
src/soc/decoder/power_enums.py
src/soc/decoder/test/test_decoder_gas.py
src/soc/decoder/test/test_power_decoder.py
src/soc/experiment/alu_hier.py
src/soc/experiment/compalu.py
src/soc/experiment/compldst_multi.py
src/soc/experiment/l0_cache.py
src/soc/experiment/score6600.py
src/soc/experiment/score6600_multi.py
src/soc/experiment/sim.py
src/soc/experiment/test/test_compalu_multi.py
src/soc/fu/alu/alu_input_record.py
src/soc/fu/alu/formal/proof_input_stage.py
src/soc/fu/alu/formal/proof_main_stage.py
src/soc/fu/alu/formal/proof_output_stage.py
src/soc/fu/alu/main_stage.py
src/soc/fu/alu/output_stage.py
src/soc/fu/alu/test/test_pipe_caller.py
src/soc/fu/branch/br_input_record.py
src/soc/fu/branch/formal/proof_input_stage.py
src/soc/fu/branch/formal/proof_main_stage.py
src/soc/fu/branch/main_stage.py
src/soc/fu/branch/test/test_pipe_caller.py
src/soc/fu/common_input_stage.py
src/soc/fu/common_output_stage.py
src/soc/fu/compunits/formal/test_compunit.py
src/soc/fu/cr/cr_input_record.py
src/soc/fu/cr/formal/proof_main_stage.py
src/soc/fu/cr/main_stage.py
src/soc/fu/div/core_stages.py
src/soc/fu/div/formal/proof_main_stage.py
src/soc/fu/div/output_stage.py
src/soc/fu/div/setup_stage.py
src/soc/fu/div/test/test_pipe_caller.py
src/soc/fu/ldst/ldst_input_record.py
src/soc/fu/ldst/test/test_pipe_caller.py
src/soc/fu/logical/formal/proof_input_stage.py
src/soc/fu/logical/formal/proof_main_stage.py
src/soc/fu/logical/logical_input_record.py
src/soc/fu/logical/main_stage.py
src/soc/fu/logical/output_stage.py
src/soc/fu/mul/formal/proof_main_stage.py
src/soc/fu/mul/mul_input_record.py
src/soc/fu/mul/post_stage.py
src/soc/fu/mul/test/test_pipe_caller.py
src/soc/fu/shift_rot/formal/proof_main_stage.py
src/soc/fu/shift_rot/main_stage.py
src/soc/fu/shift_rot/sr_input_record.py
src/soc/fu/spr/main_stage.py
src/soc/fu/spr/spr_input_record.py
src/soc/fu/spr/test/test_pipe_caller.py
src/soc/fu/trap/main_stage.py
src/soc/fu/trap/test/test_pipe_caller.py
src/soc/fu/trap/trap_input_record.py
src/soc/simple/core.py
src/soc/simple/issuer.py
src/soc/simulator/test_div_sim.py
src/soc/simulator/test_helloworld_sim.py
src/soc/simulator/test_mul_sim.py
src/soc/simulator/test_sim.py
src/soc/simulator/test_trap_sim.py