Added $anyseq cell type
authorClifford Wolf <clifford@clifford.at>
Fri, 14 Oct 2016 13:24:03 +0000 (15:24 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 14 Oct 2016 13:24:03 +0000 (15:24 +0200)
commitbdc316db50cd8b68ef096386a89c1b38793784e1
tree507341053afa28df1a753ef9de33c3d096683720
parent2733994aeba0879533cc1a871aae84497b32ff9e
Added $anyseq cell type
backends/smt2/smt2.cc
examples/smtbmc/demo7.v
frontends/ast/genrtlil.cc
frontends/ast/simplify.cc
frontends/verilog/verilog_parser.y
kernel/celltypes.h
kernel/rtlil.cc
kernel/rtlil.h
kernel/satgen.h
manual/CHAPTER_CellLib.tex
techlibs/common/simlib.v