crank A7 FPGA speed down to experiment
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 20 Mar 2022 13:40:47 +0000 (13:40 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 20 Mar 2022 13:40:47 +0000 (13:40 +0000)
commitd6ed8f60b7382bb53496a87f8a79b973bfaca693
tree73a4eddca493aad533bfcb7d5705b17a3e26b360
parentc080a6e08cd7f73744f8c2dc314f9b9786268789
crank A7 FPGA speed down to experiment
src/arty_a7.py
src/ls2.py