Add flooring division operator
authorXiretza <xiretza@xiretza.xyz>
Tue, 21 Apr 2020 10:51:58 +0000 (12:51 +0200)
committerXiretza <xiretza@xiretza.xyz>
Thu, 28 May 2020 20:59:04 +0000 (22:59 +0200)
commitedd8ff2c0778d97808869488cc7394151456c4ca
tree797418b87588ae7a69992b7f107dfd5cdfdec08d
parent17163cf43a6b6eec9aac44f6a4463dda54b8ed68
Add flooring division operator

The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
19 files changed:
backends/btor/test_cells.sh
backends/smv/test_cells.sh
backends/verilog/verilog_backend.cc
kernel/calc.cc
kernel/celledges.cc
kernel/celltypes.h
kernel/rtlil.cc
kernel/rtlil.h
kernel/satgen.h
manual/PRESENTATION_Prog.tex
passes/cmds/stat.cc
passes/memory/memory_share.cc
passes/opt/opt_expr.cc
passes/opt/opt_share.cc
passes/opt/share.cc
passes/opt/wreduce.cc
passes/tests/test_cell.cc
techlibs/common/simlib.v
techlibs/common/techmap.v