[AArch64][doc] Clarify -msve-vector-bits=128 behaviour
authorKyrylo Tkachov <kyrylo.tkachov@arm.com>
Thu, 13 Dec 2018 10:37:15 +0000 (10:37 +0000)
committerKyrylo Tkachov <ktkachov@gcc.gnu.org>
Thu, 13 Dec 2018 10:37:15 +0000 (10:37 +0000)
commitee03c51c0b62d64497eb31d630ec386df6c7299d
treecda00bd5d203054cdcf4661b86c0c9fba88eacb2
parent7cab07f0891dec03f64ae4be225f7dd5ea4c70ee
[AArch64][doc] Clarify -msve-vector-bits=128 behaviour

We've received reports about the -msve-vector-bits=128 bits being somewhat ambiguous.
It isn't clear whether -msve-vector-bits=128 forces vector-length-agnostic code or whether
-msve-vector-bits=scalable forces 128-bit vector-lengh-specific code.
The latter is a, perhaps unintuitive, reading that we want to exclude.

This patch makes it more explicit that -msve-vector-bits=128 is special and produces
vector-length *agnostic* code. In the end, I've rewritten the whole option documentation.

Checked make pdf that the output looks reasonable.

    * doc/invoke.texi (-msve-vector-bits): Clarify -msve-vector-bits=128
    behavior.

From-SVN: r267081
gcc/ChangeLog
gcc/doc/invoke.texi