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(parent: 9df2d06) | patch
connect up boundary scan to inputs/outputs
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 14 Apr 2021 10:04:31 +0000 (10:04 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 14 Apr 2021 10:04:31 +0000 (10:04 +0000)
commiteeb2d5ef99d086f4d1ae757d35613cabae478c2d
tree2ce2fc663a375c1ac39035be01e837ca0069332etree
parent9df2d06ce42a0cbbda796d51860298e85d0fe300commit | diff
connect up boundary scan to inputs/outputs
experiments10_verilog/add.py diff | blob | history