sv: support declaration in procedural for initialization
authorZachary Snow <zach@zachjs.com>
Mon, 30 Aug 2021 17:35:36 +0000 (11:35 -0600)
committerZachary Snow <zachary.j.snow@gmail.com>
Mon, 30 Aug 2021 21:19:21 +0000 (15:19 -0600)
commitf0a52e3dd275ee57a1b3ffd0a734b591bf21f668
tree3c0c7883cf1e5045701ee5c739cfd6a6a6fbbc2c
parent1dbf91a8ef3109d6573ae64fc3fd08aedc0a690d
sv: support declaration in procedural for initialization

In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.
frontends/verilog/verilog_parser.y
tests/verilog/for_decl_no_init.ys [new file with mode: 0644]
tests/verilog/for_decl_no_sv.ys [new file with mode: 0644]
tests/verilog/for_decl_shadow.sv [new file with mode: 0644]
tests/verilog/for_decl_shadow.ys [new file with mode: 0644]