RISC-V: Remove RV64E conflict
authorTsukasa OI <research_trasio@irq.a4lg.com>
Tue, 25 Jul 2023 01:02:01 +0000 (01:02 +0000)
committerTsukasa OI <research_trasio@irq.a4lg.com>
Mon, 16 Oct 2023 04:11:07 +0000 (04:11 +0000)
commitf1a0961ee09281ba3ddce1abb0541b45c4185094
tree53a657f23925d33928d13ac55d762f7ebe338e83
parentde59d50076b6558dfe21b74efc091c3f9def88fd
RISC-V: Remove RV64E conflict

Since RV32E *and* RV64E are ratified, RV64E is no longer invalid.

This commit removes a restriction that prevents making base ISA with
reduced GPRs with XLEN > 32.

bfd/ChangeLog:

* elfxx-riscv.c (riscv_parse_check_conflicts): Remove RV64E
conflict since the ratified 'E' base ISAs include RV64E.

gas/ChangeLog:

* testsuite/gas/riscv/march-fail-base-02.d: Removed.
* testsuite/gas/riscv/march-fail-base-02.l: Removed.
bfd/elfxx-riscv.c
gas/testsuite/gas/riscv/march-fail-base-02.d [deleted file]
gas/testsuite/gas/riscv/march-fail-base-02.l [deleted file]