Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 13 May 2020 18:18:06 +0000 (19:18 +0100)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Wed, 13 May 2020 18:18:30 +0000 (19:18 +0100)
commitf314a88904a5f219e4e7d555e6513799032e6ddb
tree7bc2fcea83a78d15a2cdc0564ecc227a5f0c7d28
parent751d3f1dfffbfeeed1703b010987dd6b5be8e148
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
9f/0f352016c518a90a526662879d2c7ed1c236bb [new file with mode: 0644]