Merge pull request #421 from betrusted-io/clk0_fractional
authorenjoy-digital <florent@enjoy-digital.fr>
Fri, 13 Mar 2020 13:15:24 +0000 (14:15 +0100)
committerGitHub <noreply@github.com>
Fri, 13 Mar 2020 13:15:24 +0000 (14:15 +0100)
commitf34593a17dab7ebe491d9e04dfa9c94c6a7ea753
tree357934c6d0b4d1c9fa778f63232d5b550c2951b2
parenteb9f54b2bca60c416f929acb40c7c5f7db1335d8
parent5b92bf2d575416739995b9f5905654a72fdcacb3
Merge pull request #421 from betrusted-io/clk0_fractional

add fractional division options to clk0 config on PLL
litex/soc/cores/clock.py