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(parent: ace2b5f) | patch
hdl.ir: call back from Fragment.prepare if a clock domain is missing.
authorwhitequark <whitequark@whitequark.org>
Sat, 3 Aug 2019 14:54:20 +0000 (14:54 +0000)
committerwhitequark <whitequark@whitequark.org>
Sat, 3 Aug 2019 14:54:20 +0000 (14:54 +0000)
commitfdb0c5a6bc5f2e77ded421337b17f225f72c0539
tree2033c6576cfdd071ece4f3013ccba18c9ae12a2ctree
parentace2b5ff0a0bc27bb36ba89f9a0f5ebc4202cb39commit | diff
hdl.ir: call back from Fragment.prepare if a clock domain is missing.

See #57.
nmigen/build/plat.py diff | blob | history
nmigen/compat/fhdl/verilog.py diff | blob | history
nmigen/compat/sim/__init__.py diff | blob | history
nmigen/hdl/ir.py diff | blob | history
nmigen/hdl/xfrm.py diff | blob | history
nmigen/test/test_hdl_ir.py diff | blob | history
nmigen/test/test_sim.py diff | blob | history