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(parent: affed10) | patch
Fixed Verific parser error in ice40 cell library
authorClaire Xenia Wolf <claire@clairexen.net>
Tue, 19 Oct 2021 10:33:01 +0000 (12:33 +0200)
committerClaire Xenia Wolf <claire@clairexen.net>
Tue, 19 Oct 2021 10:33:18 +0000 (12:33 +0200)
commitfe9689c136bc42dbb3ac4e4ecaaa08d7b4721ab4
tree87b44831dc87c02765f8cfedd6956559681c68actree
parentaffed103e0cb4c79afadccdafebc2a0e2a1f3150commit | diff
Fixed Verific parser error in ice40 cell library

non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
techlibs/ice40/cells_sim.v diff | blob | history