Merge pull request #1147 from YosysHQ/clifford/fix1144
authorClifford Wolf <clifford@clifford.at>
Wed, 3 Jul 2019 10:30:37 +0000 (12:30 +0200)
committerDavid Shah <dave@ds0.me>
Tue, 9 Jul 2019 17:47:08 +0000 (18:47 +0100)
commitfecd3aa2b15a20fc72d790b2437ee016ae879c14
tree6a880c886961cf36feb69a5de3099d0a9b26e249
parentd105e2f03f259e4f2be3d6d9ba970565d8422b87
Merge pull request #1147 from YosysHQ/clifford/fix1144

Improve specify dummy parser
frontends/verilog/verilog_parser.y
tests/various/specify.v
tests/various/specify.ys