+ def test_register_allocate_graphs(self):
+ fn, _arg = self.make_add_fn()
+ graphs = {} # type: dict[str, str]
+
+ def dump_graph(name, dot):
+ # type: (str, str) -> None
+ self.assertNotIn(name, graphs, "duplicate graph name")
+ graphs[name] = dot
+ allocated = allocate_registers(fn, dump_graph=dump_graph)
+ self.assertEqual(
+ repr(allocated),
+ "{"
+ "<add.outputs[0]: <I64*32>>: "
+ "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+ "<add.inp1.copy.outputs[0]: <I64*32>>: "
+ "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
+ "<add.inp0.copy.outputs[0]: <I64*32>>: "
+ "Loc(kind=LocKind.GPR, start=78, reg_len=32), "
+ "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<st.inp1.copy.outputs[0]: <I64>>: "
+ "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+ "<st.inp0.copy.outputs[0]: <I64*32>>: "
+ "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+ "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<add.out0.copy.outputs[0]: <I64*32>>: "
+ "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+ "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<ca.outputs[0]: <CA>>: "
+ "Loc(kind=LocKind.CA, start=0, reg_len=1), "
+ "<add.outputs[1]: <CA>>: "
+ "Loc(kind=LocKind.CA, start=0, reg_len=1), "
+ "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<li.out0.copy.outputs[0]: <I64*32>>: "
+ "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+ "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<li.outputs[0]: <I64*32>>: "
+ "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+ "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<ld.out0.copy.outputs[0]: <I64*32>>: "
+ "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
+ "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<ld.outputs[0]: <I64*32>>: "
+ "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+ "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<ld.inp0.copy.outputs[0]: <I64>>: "
+ "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+ "<vl.outputs[0]: <VL_MAXVL>>: "
+ "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+ "<arg.out0.copy.outputs[0]: <I64>>: "
+ "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
+ "<arg.outputs[0]: <I64>>: "
+ "Loc(kind=LocKind.GPR, start=3, reg_len=1)"
+ "}"
+ )
+ dump_graphs(self, graphs)
+ # FIXME: is_copy_related is not correct, it's missing a bunch of
+ # edges (which aren't interference edges)
+ self.assertEqual(graphs, {
+ 'initial':
+ 'graph {\n'
+ ' "0" [label = "<arg.outputs[0]: <I64>>: 0"]\n'
+ ' "1" [label = "<arg.out0.copy.outputs[0]: <I64>>: 0"]\n'
+ ' "2" [label = "<vl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "3" [label = "<ld.inp0.copy.outputs[0]: <I64>>: 0"]\n'
+ ' "4" [label = "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "5" [label = "<ld.outputs[0]: <I64*32>>: 0"]\n'
+ ' "6" [label = "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "7" [label = "<ld.out0.copy.outputs[0]: <I64*32>>: 0"]\n'
+ ' "8" [label = "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "9" [label = "<li.outputs[0]: <I64*32>>: 0"]\n'
+ ' "10" [label = "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "11" [label = "<li.out0.copy.outputs[0]: <I64*32>>: 0"]\n'
+ ' "12" [label = "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "13" [label = "<add.inp0.copy.outputs[0]: <I64*32>>: 0"]\n'
+ ' "14" [label = "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "15" [label = "<add.inp1.copy.outputs[0]: <I64*32>>: 0"]\n'
+ ' "16" [label = "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "17" [label = "<add.outputs[0]: <I64*32>>: 0"]\n'
+ ' "18" [label = "<ca.outputs[0]: <CA>>: 0\\n'
+ '<add.outputs[1]: <CA>>: 0"]\n'
+ ' "19" [label = "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "20" [label = "<add.out0.copy.outputs[0]: <I64*32>>: 0"]\n'
+ ' "21" [label = "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "22" [label = "<st.inp0.copy.outputs[0]: <I64*32>>: 0"]\n'
+ ' "23" [label = "<st.inp1.copy.outputs[0]: <I64>>: 0"]\n'
+ ' "24" [label = "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
+ ' "1" -- "3" [label = "IGEdge(is_copy_related=True)"]\n'
+ ' "1" -- "5" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "1" -- "7" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "1" -- "9" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "1" -- "11" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "1" -- "13" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "1" -- "15" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "1" -- "17" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "1" -- "20" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "1" -- "22" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "3" -- "5" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "7" -- "9" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "7" -- "11" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "11" -- "13" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "13" -- "15" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "13" -- "17" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "15" -- "17" [label = "IGEdge(is_copy_related=False)"]\n'
+ ' "22" -- "23" [label = "IGEdge(is_copy_related=False)"]\n'
+ '}'
+ })
+