+ uart_writestr("Rdly\np0: ");
+ for (size_t i = 0; i < 8; i++) {
+ profile2.rdly_p0 = i;
+ gram_load_calibration(&ctx, &profile2);
+ gram_reset_burstdet(&ctx);
+ for (size_t j = 0; j < 128; j++) {
+ tmp = ram[j];
+ }
+ if (gram_read_burstdet(&ctx, 0)) {
+ uart_writestr("1");
+ } else {
+ uart_writestr("0");
+ }
+ }
+ uart_writestr("\n");
+
+ uart_writestr("Rdly\np1: ");
+ for (size_t i = 0; i < 8; i++) {
+ profile2.rdly_p1 = i;
+ gram_load_calibration(&ctx, &profile2);
+ gram_reset_burstdet(&ctx);
+ for (size_t j = 0; j < 128; j++) {
+ tmp = ram[j];
+ }
+ if (gram_read_burstdet(&ctx, 1)) {
+ uart_writestr("1");
+ } else {
+ uart_writestr("0");
+ }
+ }
+ uart_writestr("\n");
+