+ data_map.add_window(self._cache.intr_bus.memory_map)
+
+ self._data_bus.memory_map = data_map
+
+ # Control path : bridge -> LiteDRAM control port
+
+ self._ctrl_bus = self.window(
+ addr_width = core._ctrl_bus.addr_width,
+ data_width = data_width,
+ granularity = granularity,
+ addr = core.size,
+ )
+ ctrl_map = MemoryMap(
+ addr_width = self._ctrl_bus.addr_width + granularity_bits,
+ data_width = granularity,
+ alignment = 0,
+ )
+
+ ctrl_map.add_window(core.ctrl_bus.memory_map)