- in_valid: Signal()
- input. true when the data inputs (`n` and `d`) are valid.
- data transfer in occurs when `in_valid & in_ready`.
- in_ready: Signal()
- output. true when this FSM is ready to accept input.
- data transfer in occurs when `in_valid & in_ready`.
- n: Signal(shape.n_width)
- numerator in, the value must be small enough that `q` and `r` don't
- overflow. having `n_width == width` is sufficient.
- d: Signal(shape.width)
- denominator in, must be non-zero.
- q: Signal(shape.width)
- quotient out.
- r: Signal(shape.width)
- remainder out.
- out_valid: Signal()
- output. true when the data outputs (`q` and `r`) are valid
- (or are junk because the inputs were out of range).
- data transfer out occurs when `out_valid & out_ready`.
- out_ready: Signal()
- input. true when the output can be read.
- data transfer out occurs when `out_valid & out_ready`.
+ pspec:
+ pipe-spec
+ empty: Signal()
+ true if nothing is stored in `self.saved_state`
+ saved_state: CLDivRemState()
+ the saved state that is currently being worked on.