- register_access_t access = register_access[n];
- switch (access.clss) {
- case RC_XPR:
- p->state.XPR.write(access.index, value);
- break;
- case RC_PC:
- p->state.pc = value;
- break;
- case RC_FPR:
- p->state.FPR.write(access.index, value);
- break;
- case RC_CSR:
- try {
- p->set_csr(access.index, value);
- } catch(trap_t& t) {
- return send_packet("EFF");
- }
- break;
+ if (n >= REG_XPR0 && n <= REG_XPR31) {
+ p->state.XPR.write(n - REG_XPR0, value);
+ } else if (n == REG_PC) {
+ p->state.pc = value;
+ } else if (n >= REG_FPR0 && n <= REG_FPR31) {
+ p->state.FPR.write(n - REG_FPR0, value);
+ } else if (n >= REG_CSR0 && n <= REG_CSR4095) {
+ try {
+ p->set_csr(n - REG_CSR0, value);
+ } catch(trap_t& t) {
+ return send_packet("EFF");
+ }
+ } else {
+ return send_packet("E07");