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add parent_pspec everywhere
author
Jacob Lifshay
<programmerjake@gmail.com>
Thu, 9 Dec 2021 03:56:36 +0000
(19:56 -0800)
committer
Jacob Lifshay
<programmerjake@gmail.com>
Thu, 9 Dec 2021 03:59:25 +0000
(19:59 -0800)
30 files changed:
src/soc/experiment/alu_hier.py
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src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
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src/soc/fu/alu/formal/proof_input_stage.py
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src/soc/fu/alu/formal/proof_main_stage.py
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src/soc/fu/alu/formal/proof_output_stage.py
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src/soc/fu/alu/test/test_pipe_caller.py
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src/soc/fu/branch/formal/proof_input_stage.py
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src/soc/fu/branch/formal/proof_main_stage.py
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src/soc/fu/branch/test/test_pipe_caller.py
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src/soc/fu/compunits/compunits.py
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src/soc/fu/cr/formal/proof_main_stage.py
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src/soc/fu/cr/test/test_pipe_caller.py
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src/soc/fu/div/pipe_data.py
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src/soc/fu/div/test/helper.py
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src/soc/fu/div/test/test_pipe_ilang.py
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src/soc/fu/logical/formal/proof_input_stage.py
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src/soc/fu/logical/formal/proof_main_stage.py
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src/soc/fu/logical/test/test_pipe_caller.py
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src/soc/fu/mmu/test/test_non_production_core.py
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src/soc/fu/mmu/test/test_pipe_caller.py
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src/soc/fu/mul/formal/proof_main_stage.py
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src/soc/fu/mul/test/helper.py
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src/soc/fu/mul/test/test_pipe_ilang.py
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src/soc/fu/pipe_data.py
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src/soc/fu/shift_rot/formal/proof_main_stage.py
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src/soc/fu/shift_rot/test/test_pipe_caller.py
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src/soc/fu/spr/formal/proof_main_stage.py
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src/soc/fu/spr/test/test_pipe_caller.py
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src/soc/fu/trap/formal/proof_main_stage.py
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src/soc/fu/trap/test/test_pipe_caller.py
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diff --git
a/src/soc/experiment/alu_hier.py
b/src/soc/experiment/alu_hier.py
index d4ed5aaa399d3b87363a7cd9ee6cd18483c0454b..459bbd951cb41a35e5f06089162e365fd8b03d9b 100644
(file)
--- a/
src/soc/experiment/alu_hier.py
+++ b/
src/soc/experiment/alu_hier.py
@@
-218,8
+218,8
@@
class ALUFunctionUnit(FunctionUnitBaseSingle):
# class ALUFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.ALU
# class ALUFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.ALU
- def __init__(self, idx):
- super().__init__(ALUPipeSpec, ALU, 1)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(ALUPipeSpec, ALU, 1
, parent_pspec
)
class ALU(Elaboratable):
class ALU(Elaboratable):
diff --git
a/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
b/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
index 5f7ee4414856ebba5d025eb919b72e88d2da9012..81d21c180962966a147b8d38b957cb5804d99eac 100644
(file)
--- a/
src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
+++ b/
src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
@@
-139,7
+139,7
@@
class TestLDSTCompUnitRegSpecMMUFSM(LDSTCompUnit):
self.mmu = MMU()
self.mmu = MMU()
- pipe_spec = MMUPipeSpec(id_wid=2)
+ pipe_spec = MMUPipeSpec(id_wid=2
, parent_pspec=None
)
self.fsm = FSMMMUStage(pipe_spec)
self.fsm.set_ldst_interface(ldst)
self.fsm = FSMMMUStage(pipe_spec)
self.fsm.set_ldst_interface(ldst)
diff --git
a/src/soc/fu/alu/formal/proof_input_stage.py
b/src/soc/fu/alu/formal/proof_input_stage.py
index 001c063e0a1ec05a939162b6bab5aa1702dec0ec..ba65373b646dcdde5a90e89161aae7bdea65a578 100644
(file)
--- a/
src/soc/fu/alu/formal/proof_input_stage.py
+++ b/
src/soc/fu/alu/formal/proof_input_stage.py
@@
-32,7
+32,7
@@
class Driver(Elaboratable):
recwidth += width
comb += p.eq(AnyConst(width))
recwidth += width
comb += p.eq(AnyConst(width))
- pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth)
+ pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth
, parent_pspec=None
)
m.submodules.dut = dut = ALUInputStage(pspec)
a = Signal(64)
m.submodules.dut = dut = ALUInputStage(pspec)
a = Signal(64)
diff --git
a/src/soc/fu/alu/formal/proof_main_stage.py
b/src/soc/fu/alu/formal/proof_main_stage.py
index 655ca4700b104f6193f254024acd20200b432839..de8dc54f1c82ea18eb768e40ec183fab119e5049 100644
(file)
--- a/
src/soc/fu/alu/formal/proof_main_stage.py
+++ b/
src/soc/fu/alu/formal/proof_main_stage.py
@@
-37,7
+37,7
@@
class Driver(Elaboratable):
width = p.width
comb += p.eq(AnyConst(width))
width = p.width
comb += p.eq(AnyConst(width))
- pspec = ALUPipeSpec(id_wid=2)
+ pspec = ALUPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.dut = dut = ALUMainStage(pspec)
# convenience variables
m.submodules.dut = dut = ALUMainStage(pspec)
# convenience variables
diff --git
a/src/soc/fu/alu/formal/proof_output_stage.py
b/src/soc/fu/alu/formal/proof_output_stage.py
index e20aa1ebd2cf5f4381b3ad16e0a479ca2345b589..eb6f45719553b8545111595cb0d7964a7a45872f 100644
(file)
--- a/
src/soc/fu/alu/formal/proof_output_stage.py
+++ b/
src/soc/fu/alu/formal/proof_output_stage.py
@@
-38,7
+38,7
@@
class Driver(Elaboratable):
recwidth += width
comb += p.eq(AnyConst(width))
recwidth += width
comb += p.eq(AnyConst(width))
- pspec = ALUPipeSpec(id_wid=2)
+ pspec = ALUPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.dut = dut = ALUOutputStage(pspec)
o = Signal(64)
m.submodules.dut = dut = ALUOutputStage(pspec)
o = Signal(64)
diff --git
a/src/soc/fu/alu/test/test_pipe_caller.py
b/src/soc/fu/alu/test/test_pipe_caller.py
index f40187f461f70d5edcebe02dedb9dc1cdcef6113..704fc69a59eb8fdd30237f60a90d9a9fef4b978c 100644
(file)
--- a/
src/soc/fu/alu/test/test_pipe_caller.py
+++ b/
src/soc/fu/alu/test/test_pipe_caller.py
@@
-51,7
+51,7
@@
def set_alu_inputs(alu, dec2, sim):
class ALUIAllCases(ALUTestCase):
def case_ilang(self):
class ALUIAllCases(ALUTestCase):
def case_ilang(self):
- pspec = ALUPipeSpec(id_wid=2)
+ pspec = ALUPipeSpec(id_wid=2
, parent_pspec=None
)
alu = ALUBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("alu_pipeline.il", "w") as f:
alu = ALUBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("alu_pipeline.il", "w") as f:
@@
-124,7
+124,7
@@
class TestRunner(unittest.TestCase):
pdecode, opkls, fn_name)
pdecode = pdecode2.dec
pdecode, opkls, fn_name)
pdecode = pdecode2.dec
- pspec = ALUPipeSpec(id_wid=2)
+ pspec = ALUPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.alu = alu = ALUBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
m.submodules.alu = alu = ALUBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
diff --git
a/src/soc/fu/branch/formal/proof_input_stage.py
b/src/soc/fu/branch/formal/proof_input_stage.py
index 79d3c662f60167bd27d34aca6240550fc8cd9fec..739d3b20fe8a15806315c546deef5460a0d5653a 100644
(file)
--- a/
src/soc/fu/branch/formal/proof_input_stage.py
+++ b/
src/soc/fu/branch/formal/proof_input_stage.py
@@
-32,7
+32,7
@@
class Driver(Elaboratable):
recwidth += width
comb += p.eq(AnyConst(width))
recwidth += width
comb += p.eq(AnyConst(width))
- pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth)
+ pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth
, parent_pspec=None
)
m.submodules.dut = dut = ALUInputStage(pspec)
a = Signal(64)
m.submodules.dut = dut = ALUInputStage(pspec)
a = Signal(64)
diff --git
a/src/soc/fu/branch/formal/proof_main_stage.py
b/src/soc/fu/branch/formal/proof_main_stage.py
index 5d940b1ad873992c33890bb86b74526a0b5ca54e..0f58e1c049d130e3cc1b46ddccd0bbbc1a6f53dc 100644
(file)
--- a/
src/soc/fu/branch/formal/proof_main_stage.py
+++ b/
src/soc/fu/branch/formal/proof_main_stage.py
@@
-39,7
+39,7
@@
class Driver(Elaboratable):
recwidth += width
comb += p.eq(AnyConst(width))
recwidth += width
comb += p.eq(AnyConst(width))
- pspec = BranchPipeSpec(id_wid=2)
+ pspec = BranchPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.dut = dut = BranchMainStage(pspec)
# convenience aliases
m.submodules.dut = dut = BranchMainStage(pspec)
# convenience aliases
diff --git
a/src/soc/fu/branch/test/test_pipe_caller.py
b/src/soc/fu/branch/test/test_pipe_caller.py
index 0b701ae85b0ddcc550cf8f1dfe1a68a4c086d4cf..794d86da5a39ea1b5815750f3cfdca2be764d113 100644
(file)
--- a/
src/soc/fu/branch/test/test_pipe_caller.py
+++ b/
src/soc/fu/branch/test/test_pipe_caller.py
@@
-50,7
+50,7
@@
def get_cu_inputs(dec2, sim):
class BranchAllCases(BranchTestCase):
def case_ilang(self):
class BranchAllCases(BranchTestCase):
def case_ilang(self):
- pspec = BranchPipeSpec(id_wid=2)
+ pspec = BranchPipeSpec(id_wid=2
, parent_pspec=None
)
alu = BranchBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("branch_pipeline.il", "w") as f:
alu = BranchBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("branch_pipeline.il", "w") as f:
@@
-70,7
+70,7
@@
class TestRunner(unittest.TestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
pdecode = pdecode2.dec
m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
pdecode = pdecode2.dec
- pspec = BranchPipeSpec(id_wid=2)
+ pspec = BranchPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.branch = branch = BranchBasePipe(pspec)
comb += branch.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
m.submodules.branch = branch = BranchBasePipe(pspec)
comb += branch.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
diff --git
a/src/soc/fu/compunits/compunits.py
b/src/soc/fu/compunits/compunits.py
index 773bf81448cdc63250f3279a939e33234242b3aa..ee9f49817ddcd7826a8322754b29e142ece74070 100644
(file)
--- a/
src/soc/fu/compunits/compunits.py
+++ b/
src/soc/fu/compunits/compunits.py
@@
-115,9
+115,10
@@
class FunctionUnitBaseSingle(MultiCompUnit):
to actually read (and write) the correct register number
"""
to actually read (and write) the correct register number
"""
- def __init__(self, speckls, pipekls, idx):
+ def __init__(self, speckls, pipekls, idx
, parent_pspec
):
alu_name = "alu_%s%d" % (self.fnunit.name.lower(), idx)
alu_name = "alu_%s%d" % (self.fnunit.name.lower(), idx)
- pspec = speckls(id_wid=2) # spec (NNNPipeSpec instance)
+ # spec (NNNPipeSpec instance)
+ pspec = speckls(id_wid=2, parent_pspec=parent_pspec)
opsubset = pspec.opsubsetkls # get the operand subset class
regspec = pspec.regspec # get the regspec
alu = pipekls(pspec) # create actual NNNBasePipe
opsubset = pspec.opsubsetkls # get the operand subset class
regspec = pspec.regspec # get the regspec
alu = pipekls(pspec) # create actual NNNBasePipe
@@
-154,9
+155,11
@@
class FunctionUnitBaseMulti(ReservationStations2):
ideal (it could be a lot neater) but works for now.
"""
ideal (it could be a lot neater) but works for now.
"""
- def __init__(self, speckls, pipekls, num_rows):
+ def __init__(self, speckls, pipekls, num_rows
, parent_pspec
):
id_wid = num_rows.bit_length()
id_wid = num_rows.bit_length()
- pspec = speckls(id_wid=id_wid) # spec (NNNPipeSpec instance)
+
+ # spec (NNNPipeSpec instance)
+ pspec = speckls(id_wid=id_wid, parent_pspec=parent_pspec)
opsubset = pspec.opsubsetkls # get the operand subset class
regspec = pspec.regspec # get the regspec
alu = pipekls(pspec) # create actual NNNBasePipe
opsubset = pspec.opsubsetkls # get the operand subset class
regspec = pspec.regspec # get the regspec
alu = pipekls(pspec) # create actual NNNBasePipe
@@
-191,83
+194,83
@@
class FunctionUnitBaseMulti(ReservationStations2):
class ALUFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.ALU
class ALUFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.ALU
- def __init__(self, num_rses):
- super().__init__(ALUPipeSpec, ALUBasePipe, num_rses)
+ def __init__(self, num_rses
, parent_pspec
):
+ super().__init__(ALUPipeSpec, ALUBasePipe, num_rses
, parent_pspec
)
# class LogicalFunctionUnit(FunctionUnitBaseSingle):
class LogicalFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.LOGICAL
# class LogicalFunctionUnit(FunctionUnitBaseSingle):
class LogicalFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.LOGICAL
- def __init__(self, idx):
- super().__init__(LogicalPipeSpec, LogicalBasePipe, idx)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(LogicalPipeSpec, LogicalBasePipe, idx
, parent_pspec
)
# class CRFunctionUnit(FunctionUnitBaseSingle):
class CRFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.CR
# class CRFunctionUnit(FunctionUnitBaseSingle):
class CRFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.CR
- def __init__(self, idx):
- super().__init__(CRPipeSpec, CRBasePipe, idx)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(CRPipeSpec, CRBasePipe, idx
, parent_pspec
)
# class BranchFunctionUnit(FunctionUnitBaseSingle):
class BranchFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.BRANCH
# class BranchFunctionUnit(FunctionUnitBaseSingle):
class BranchFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.BRANCH
- def __init__(self, idx):
- super().__init__(BranchPipeSpec, BranchBasePipe, idx)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(BranchPipeSpec, BranchBasePipe, idx
, parent_pspec
)
# class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
class ShiftRotFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.SHIFT_ROT
# class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
class ShiftRotFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.SHIFT_ROT
- def __init__(self, idx):
- super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe, idx)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe, idx
, parent_pspec
)
class DivFSMFunctionUnit(FunctionUnitBaseSingle):
fnunit = Function.DIV
class DivFSMFunctionUnit(FunctionUnitBaseSingle):
fnunit = Function.DIV
- def __init__(self, idx):
- super().__init__(DivPipeSpecFSMDivCore, DivBasePipe, idx)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(DivPipeSpecFSMDivCore, DivBasePipe, idx
, parent_pspec
)
class MMUFSMFunctionUnit(FunctionUnitBaseSingle):
fnunit = Function.MMU
class MMUFSMFunctionUnit(FunctionUnitBaseSingle):
fnunit = Function.MMU
- def __init__(self, idx):
- super().__init__(MMUPipeSpec, FSMMMUStage, idx)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(MMUPipeSpec, FSMMMUStage, idx
, parent_pspec
)
class DivPipeFunctionUnit(FunctionUnitBaseSingle):
fnunit = Function.DIV
class DivPipeFunctionUnit(FunctionUnitBaseSingle):
fnunit = Function.DIV
- def __init__(self, idx):
- super().__init__(DivPipeSpecDivPipeCore, DivBasePipe, idx)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(DivPipeSpecDivPipeCore, DivBasePipe, idx
, parent_pspec
)
# class MulFunctionUnit(FunctionUnitBaseSingle):
class MulFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.MUL
# class MulFunctionUnit(FunctionUnitBaseSingle):
class MulFunctionUnit(FunctionUnitBaseMulti):
fnunit = Function.MUL
- def __init__(self, idx):
- super().__init__(MulPipeSpec, MulBasePipe, idx)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(MulPipeSpec, MulBasePipe, idx
, parent_pspec
)
class TrapFunctionUnit(FunctionUnitBaseSingle):
fnunit = Function.TRAP
class TrapFunctionUnit(FunctionUnitBaseSingle):
fnunit = Function.TRAP
- def __init__(self, idx):
- super().__init__(TrapPipeSpec, TrapBasePipe, idx)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(TrapPipeSpec, TrapBasePipe, idx
, parent_pspec
)
class SPRFunctionUnit(FunctionUnitBaseSingle):
fnunit = Function.SPR
class SPRFunctionUnit(FunctionUnitBaseSingle):
fnunit = Function.SPR
- def __init__(self, idx):
- super().__init__(SPRPipeSpec, SPRBasePipe, idx)
+ def __init__(self, idx
, parent_pspec
):
+ super().__init__(SPRPipeSpec, SPRBasePipe, idx
, parent_pspec
)
# special-case: LD/ST conforms to the CompUnit API but is not a pipeline
# special-case: LD/ST conforms to the CompUnit API but is not a pipeline
@@
-275,9
+278,10
@@
class SPRFunctionUnit(FunctionUnitBaseSingle):
class LDSTFunctionUnit(LDSTCompUnit):
fnunit = Function.LDST
class LDSTFunctionUnit(LDSTCompUnit):
fnunit = Function.LDST
- def __init__(self, pi, awid, idx):
+ def __init__(self, pi, awid, idx
, parent_pspec
):
alu_name = "ldst_%s%d" % (self.fnunit.name.lower(), idx)
alu_name = "ldst_%s%d" % (self.fnunit.name.lower(), idx)
- pspec = LDSTPipeSpec(id_wid=2) # spec (NNNPipeSpec instance)
+ # spec (NNNPipeSpec instance)
+ pspec = LDSTPipeSpec(id_wid=2, parent_pspec=parent_pspec)
opsubset = pspec.opsubsetkls # get the operand subset class
regspec = pspec.regspec # get the regspec
self.opsubsetkls = opsubset
opsubset = pspec.opsubsetkls # get the operand subset class
regspec = pspec.regspec # get the regspec
self.opsubsetkls = opsubset
@@
-336,13
+340,14
@@
class AllFunctionUnits(Elaboratable):
for name, qty in units.items():
kls = alus[name]
if issubclass(kls, FunctionUnitBaseMulti):
for name, qty in units.items():
kls = alus[name]
if issubclass(kls, FunctionUnitBaseMulti):
- fu = kls(qty) # create just the one ALU but many "fronts"
+ # create just the one ALU but many "fronts"
+ fu = kls(qty, parent_pspec=pspec)
self.actual_alus[name] = fu # to be made a module of AllFUs
for i in range(qty):
self.fus["%s%d" % (name, i)] = fu.cu[i]
else:
for i in range(qty):
self.actual_alus[name] = fu # to be made a module of AllFUs
for i in range(qty):
self.fus["%s%d" % (name, i)] = fu.cu[i]
else:
for i in range(qty):
- self.fus["%s%d" % (name, i)] = kls(i)
+ self.fus["%s%d" % (name, i)] = kls(i
, parent_pspec=pspec
)
# debug print for MMU ALU
if microwatt_mmu:
# debug print for MMU ALU
if microwatt_mmu:
@@
-354,7
+359,7
@@
class AllFunctionUnits(Elaboratable):
return
print("pilist", pilist)
for i, pi in enumerate(pilist):
return
print("pilist", pilist)
for i, pi in enumerate(pilist):
- self.fus["ldst%d" % (i)] = LDSTFunctionUnit(pi, addrwid, i)
+ self.fus["ldst%d" % (i)] = LDSTFunctionUnit(pi, addrwid, i
, pspec
)
# extract exceptions from any FunctionUnits for easy access
self.excs = {}
# extract exceptions from any FunctionUnits for easy access
self.excs = {}
diff --git
a/src/soc/fu/cr/formal/proof_main_stage.py
b/src/soc/fu/cr/formal/proof_main_stage.py
index 0aebcbd717a43a32983ad8997f11a87118eae2b2..fa44c4d3fb685b7f89bcacca12beafb8b5ef65a1 100644
(file)
--- a/
src/soc/fu/cr/formal/proof_main_stage.py
+++ b/
src/soc/fu/cr/formal/proof_main_stage.py
@@
-37,7
+37,7
@@
class Driver(Elaboratable):
recwidth += width
comb += p.eq(AnyConst(width))
recwidth += width
comb += p.eq(AnyConst(width))
- pspec = ALUPipeSpec(id_wid=2)
+ pspec = ALUPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.dut = dut = CRMainStage(pspec)
full_cr_in = Signal(32)
m.submodules.dut = dut = CRMainStage(pspec)
full_cr_in = Signal(32)
diff --git
a/src/soc/fu/cr/test/test_pipe_caller.py
b/src/soc/fu/cr/test/test_pipe_caller.py
index 158c89cb5f965ee8592f56922039375e30d20c9a..9a92d2d6dbdacfdf1478ac99a82ce839245d97ef 100644
(file)
--- a/
src/soc/fu/cr/test/test_pipe_caller.py
+++ b/
src/soc/fu/cr/test/test_pipe_caller.py
@@
-24,7
+24,7
@@
from openpower.test.cr.cr_cases import CRTestCase
class CRIlangCase(TestAccumulatorBase):
def case_ilang(self):
class CRIlangCase(TestAccumulatorBase):
def case_ilang(self):
- pspec = CRPipeSpec(id_wid=2)
+ pspec = CRPipeSpec(id_wid=2
, parent_pspec=None
)
alu = CRBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("cr_pipeline.il", "w") as f:
alu = CRBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("cr_pipeline.il", "w") as f:
@@
-144,7
+144,7
@@
class TestRunner(unittest.TestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
pdecode = pdecode2.dec
m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
pdecode = pdecode2.dec
- pspec = CRPipeSpec(id_wid=2)
+ pspec = CRPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.alu = alu = CRBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
m.submodules.alu = alu = CRBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
diff --git
a/src/soc/fu/div/pipe_data.py
b/src/soc/fu/div/pipe_data.py
index 4c70fdf177d35e8d18144cfec25751a82563b43d..f79f980691510a430caf995b57ec08b0122f4e51 100644
(file)
--- a/
src/soc/fu/div/pipe_data.py
+++ b/
src/soc/fu/div/pipe_data.py
@@
-129,8
+129,8
@@
class DivPipeKind(enum.Enum):
class DivPipeSpec(CommonPipeSpec):
class DivPipeSpec(CommonPipeSpec):
- def __init__(self, id_wid, div_pipe_kind):
- super().__init__(id_wid=id_wid)
+ def __init__(self, id_wid,
parent_pspec,
div_pipe_kind):
+ super().__init__(id_wid=id_wid
, parent_pspec=parent_pspec
)
self.div_pipe_kind = div_pipe_kind
self.core_config = div_pipe_kind.config.core_config
self.div_pipe_kind = div_pipe_kind
self.core_config = div_pipe_kind.config.core_config
@@
-139,18
+139,24
@@
class DivPipeSpec(CommonPipeSpec):
class DivPipeSpecDivPipeCore(DivPipeSpec):
class DivPipeSpecDivPipeCore(DivPipeSpec):
- def __init__(self, id_wid):
- super().__init__(id_wid=id_wid, div_pipe_kind=DivPipeKind.DivPipeCore)
+ def __init__(self, id_wid, parent_pspec):
+ super().__init__(id_wid=id_wid,
+ parent_pspec=parent_pspec,
+ div_pipe_kind=DivPipeKind.DivPipeCore)
class DivPipeSpecFSMDivCore(DivPipeSpec):
class DivPipeSpecFSMDivCore(DivPipeSpec):
- def __init__(self, id_wid):
- super().__init__(id_wid=id_wid, div_pipe_kind=DivPipeKind.FSMDivCore)
+ def __init__(self, id_wid, parent_pspec):
+ super().__init__(id_wid=id_wid,
+ parent_pspec=parent_pspec,
+ div_pipe_kind=DivPipeKind.FSMDivCore)
class DivPipeSpecSimOnly(DivPipeSpec):
class DivPipeSpecSimOnly(DivPipeSpec):
- def __init__(self, id_wid):
- super().__init__(id_wid=id_wid, div_pipe_kind=DivPipeKind.SimOnly)
+ def __init__(self, id_wid, parent_pspec):
+ super().__init__(id_wid=id_wid,
+ parent_pspec=parent_pspec,
+ div_pipe_kind=DivPipeKind.SimOnly)
class CoreBaseData(DivInputData):
class CoreBaseData(DivInputData):
diff --git
a/src/soc/fu/div/test/helper.py
b/src/soc/fu/div/test/helper.py
index 80871fd30e5180e0e9eeeb05eb49ea7579549726..18175f12ffa17819cf4b26318fb2badf0700d6f7 100644
(file)
--- a/
src/soc/fu/div/test/helper.py
+++ b/
src/soc/fu/div/test/helper.py
@@
-163,7
+163,8
@@
class DivTestHelper(unittest.TestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
+ pspec = DivPipeSpec(
+ id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=None)
m.submodules.alu = alu = DivBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
m.submodules.alu = alu = DivBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
diff --git
a/src/soc/fu/div/test/test_pipe_ilang.py
b/src/soc/fu/div/test/test_pipe_ilang.py
index a5b343910827a6f1ddebc43492b68b4fca4dd899..a9f0cb27cfe7cf091fb4410d8efeb85937af8519 100644
(file)
--- a/
src/soc/fu/div/test/test_pipe_ilang.py
+++ b/
src/soc/fu/div/test/test_pipe_ilang.py
@@
-6,7
+6,8
@@
from soc.fu.div.pipeline import DivBasePipe
class TestPipeIlang(unittest.TestCase):
def write_ilang(self, div_pipe_kind):
class TestPipeIlang(unittest.TestCase):
def write_ilang(self, div_pipe_kind):
- pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
+ pspec = DivPipeSpec(
+ id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=None)
alu = DivBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:
alu = DivBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:
diff --git
a/src/soc/fu/logical/formal/proof_input_stage.py
b/src/soc/fu/logical/formal/proof_input_stage.py
index b0b70d381aa69eecb46c802de055d4cc72de581b..aa9b937d937ac52061912f994b295c7c7d4b1f6c 100644
(file)
--- a/
src/soc/fu/logical/formal/proof_input_stage.py
+++ b/
src/soc/fu/logical/formal/proof_input_stage.py
@@
-32,7
+32,7
@@
class Driver(Elaboratable):
recwidth += width
comb += p.eq(AnyConst(width))
recwidth += width
comb += p.eq(AnyConst(width))
- pspec = ALUPipeSpec(id_wid=2)
+ pspec = ALUPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.dut = dut = ALUInputStage(pspec)
a = Signal(64)
m.submodules.dut = dut = ALUInputStage(pspec)
a = Signal(64)
diff --git
a/src/soc/fu/logical/formal/proof_main_stage.py
b/src/soc/fu/logical/formal/proof_main_stage.py
index deac8b752a7603458fc3416789bf23e6a58894ad..87d87283de4563e7c0ec2a8f6646159d601da4fc 100644
(file)
--- a/
src/soc/fu/logical/formal/proof_main_stage.py
+++ b/
src/soc/fu/logical/formal/proof_main_stage.py
@@
-47,7
+47,7
@@
class Driver(Elaboratable):
width = p.width
comb += p.eq(AnyConst(width))
width = p.width
comb += p.eq(AnyConst(width))
- pspec = ALUPipeSpec(id_wid=2)
+ pspec = ALUPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.dut = dut = LogicalMainStage(pspec)
# convenience variables
m.submodules.dut = dut = LogicalMainStage(pspec)
# convenience variables
diff --git
a/src/soc/fu/logical/test/test_pipe_caller.py
b/src/soc/fu/logical/test/test_pipe_caller.py
index cd26976e5f5d3833c878f665d68e628ad1a65046..5ecbe2303bd1ca8b35d81801ad36ab63de99f4c3 100644
(file)
--- a/
src/soc/fu/logical/test/test_pipe_caller.py
+++ b/
src/soc/fu/logical/test/test_pipe_caller.py
@@
-51,7
+51,7
@@
def set_alu_inputs(alu, dec2, sim):
class LogicalIlangCase(TestAccumulatorBase):
def case_ilang(self):
class LogicalIlangCase(TestAccumulatorBase):
def case_ilang(self):
- pspec = LogicalPipeSpec(id_wid=2)
+ pspec = LogicalPipeSpec(id_wid=2
, parent_pspec=None
)
alu = LogicalBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("logical_pipeline.il", "w") as f:
alu = LogicalBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("logical_pipeline.il", "w") as f:
@@
-116,7
+116,7
@@
class TestRunner(FHDLTestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- pspec = LogicalPipeSpec(id_wid=2)
+ pspec = LogicalPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.alu = alu = LogicalBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
m.submodules.alu = alu = LogicalBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
diff --git
a/src/soc/fu/mmu/test/test_non_production_core.py
b/src/soc/fu/mmu/test/test_non_production_core.py
index a99579900504d5a29703853a012f3cbfd99ed4ef..e234ac22f524d9262a4085506aa19b91e7958d2b 100644
(file)
--- a/
src/soc/fu/mmu/test/test_non_production_core.py
+++ b/
src/soc/fu/mmu/test/test_non_production_core.py
@@
-50,7
+50,7
@@
class MMUTestCase(TestAccumulatorBase):
initial_regs, initial_sprs)
# def case_ilang(self):
initial_regs, initial_sprs)
# def case_ilang(self):
- # pspec = SPRPipeSpec(id_wid=2)
+ # pspec = SPRPipeSpec(id_wid=2
, parent_pspec=None
)
# alu = SPRBasePipe(pspec)
# vl = rtlil.convert(alu, ports=alu.ports())
# with open("trap_pipeline.il", "w") as f:
# alu = SPRBasePipe(pspec)
# vl = rtlil.convert(alu, ports=alu.ports())
# with open("trap_pipeline.il", "w") as f:
diff --git
a/src/soc/fu/mmu/test/test_pipe_caller.py
b/src/soc/fu/mmu/test/test_pipe_caller.py
index 70c853ebf172b61b5299949ddbd1e26c19d69316..8f36cfd8ae82cfc1eaafdcc4735a2b448f84dc64 100644
(file)
--- a/
src/soc/fu/mmu/test/test_pipe_caller.py
+++ b/
src/soc/fu/mmu/test/test_pipe_caller.py
@@
-73,7
+73,7
@@
def check_fsm_outputs(fsm, pdecode2, sim, code):
class MMUIlangCase(TestAccumulatorBase):
# def case_ilang(self):
class MMUIlangCase(TestAccumulatorBase):
# def case_ilang(self):
- # pspec = SPRPipeSpec(id_wid=2)
+ # pspec = SPRPipeSpec(id_wid=2
, parent_pspec=None
)
# alu = SPRBasePipe(pspec)
# vl = rtlil.convert(alu, ports=alu.ports())
# with open("trap_pipeline.il", "w") as f:
# alu = SPRBasePipe(pspec)
# vl = rtlil.convert(alu, ports=alu.ports())
# with open("trap_pipeline.il", "w") as f:
@@
-220,7
+220,7
@@
class TestRunner(unittest.TestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- pipe_spec = MMUPipeSpec(id_wid=2)
+ pipe_spec = MMUPipeSpec(id_wid=2
, parent_pspec=None
)
ldst = LoadStore1(pspec)
fsm = FSMMMUStage(pipe_spec)
fsm.set_ldst_interface(ldst)
ldst = LoadStore1(pspec)
fsm = FSMMMUStage(pipe_spec)
fsm.set_ldst_interface(ldst)
diff --git
a/src/soc/fu/mul/formal/proof_main_stage.py
b/src/soc/fu/mul/formal/proof_main_stage.py
index 0b68c14416634863b126956d504d703b503cdee4..a78294606b82f5c0a3aaced9051d8ee5eeeb6fe3 100644
(file)
--- a/
src/soc/fu/mul/formal/proof_main_stage.py
+++ b/
src/soc/fu/mul/formal/proof_main_stage.py
@@
-84,7
+84,7
@@
class Driver(Elaboratable):
# set up the mul stages. do not add them to m.submodules, this
# is handled by StageChain.setup().
# set up the mul stages. do not add them to m.submodules, this
# is handled by StageChain.setup().
- pspec = MulPipeSpec(id_wid=2)
+ pspec = MulPipeSpec(id_wid=2
, parent_pspec=None
)
pipe1 = MulMainStage1(pspec)
pipe2 = MulMainStage2(pspec)
pipe3 = MulMainStage3(pspec)
pipe1 = MulMainStage1(pspec)
pipe2 = MulMainStage2(pspec)
pipe3 = MulMainStage3(pspec)
diff --git
a/src/soc/fu/mul/test/helper.py
b/src/soc/fu/mul/test/helper.py
index bb9d8d8490235901a78cb1dd3fee08fda5c66ed3..4528f408b96ed5974d3d3788087a893375d8161b 100644
(file)
--- a/
src/soc/fu/mul/test/helper.py
+++ b/
src/soc/fu/mul/test/helper.py
@@
-146,7
+146,7
@@
class MulTestHelper(unittest.TestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
pdecode = pdecode2.dec
m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
pdecode = pdecode2.dec
- pspec = MulPipeSpec(id_wid=2)
+ pspec = MulPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.alu = alu = MulBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
m.submodules.alu = alu = MulBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
diff --git
a/src/soc/fu/mul/test/test_pipe_ilang.py
b/src/soc/fu/mul/test/test_pipe_ilang.py
index 22af35ba90037441175670866306bdd1c6743c82..c6ffabebffef42d195635bc8f9b3eb190231b64f 100644
(file)
--- a/
src/soc/fu/mul/test/test_pipe_ilang.py
+++ b/
src/soc/fu/mul/test/test_pipe_ilang.py
@@
-6,7
+6,7
@@
from soc.fu.mul.pipeline import MulBasePipe
class TestPipeIlang(unittest.TestCase):
def write_ilang(self):
class TestPipeIlang(unittest.TestCase):
def write_ilang(self):
- pspec = MulPipeSpec(id_wid=2)
+ pspec = MulPipeSpec(id_wid=2
, parent_pspec=None
)
alu = MulBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("mul_pipeline.il", "w") as f:
alu = MulBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("mul_pipeline.il", "w") as f:
diff --git
a/src/soc/fu/pipe_data.py
b/src/soc/fu/pipe_data.py
index b43244b387a38eec951095a40cc9cfbdcc475307..d48cf4c3456b2e9f620f91948921a4857890c41d 100644
(file)
--- a/
src/soc/fu/pipe_data.py
+++ b/
src/soc/fu/pipe_data.py
@@
-75,13
+75,14
@@
class CommonPipeSpec:
see README.md for explanation of members.
"""
see README.md for explanation of members.
"""
- def __init__(self, id_wid):
+ def __init__(self, id_wid
, parent_pspec
):
self.pipekls = SimpleHandshakeRedir
self.id_wid = id_wid
self.opkls = lambda _: self.opsubsetkls()
self.op_wid = get_rec_width(self.opkls(None)) # hmm..
self.stage = None
self.draft_bitmanip = False
self.pipekls = SimpleHandshakeRedir
self.id_wid = id_wid
self.opkls = lambda _: self.opsubsetkls()
self.op_wid = get_rec_width(self.opkls(None)) # hmm..
self.stage = None
self.draft_bitmanip = False
+ self.parent_pspec = parent_pspec
def get_pspec_draft_bitmanip(pspec):
def get_pspec_draft_bitmanip(pspec):
diff --git
a/src/soc/fu/shift_rot/formal/proof_main_stage.py
b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index 4528de0a4cb8cb3649674adb392eeee9c0cfb4ce..74b4d7db48e56e590189e062916654630ddb0c8a 100644
(file)
--- a/
src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/
src/soc/fu/shift_rot/formal/proof_main_stage.py
@@
-54,7
+54,7
@@
class Driver(Elaboratable):
comb += rec.is_signed.eq(AnyConst(rec.is_signed.width))
comb += rec.insn.eq(AnyConst(rec.insn.width))
comb += rec.is_signed.eq(AnyConst(rec.is_signed.width))
comb += rec.insn.eq(AnyConst(rec.insn.width))
- pspec = ShiftRotPipeSpec(id_wid=2)
+ pspec = ShiftRotPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.dut = dut = ShiftRotMainStage(pspec)
# convenience variables
m.submodules.dut = dut = ShiftRotMainStage(pspec)
# convenience variables
diff --git
a/src/soc/fu/shift_rot/test/test_pipe_caller.py
b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index 00bb3262e9db799cca55383aa0c181e598a400b5..3bab80818c237f00a433d10434f8ce64be44d040 100644
(file)
--- a/
src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/
src/soc/fu/shift_rot/test/test_pipe_caller.py
@@
-70,7
+70,7
@@
def set_alu_inputs(alu, dec2, sim):
class ShiftRotIlangCase(TestAccumulatorBase):
def case_ilang(self):
class ShiftRotIlangCase(TestAccumulatorBase):
def case_ilang(self):
- pspec = ShiftRotPipeSpec(id_wid=2)
+ pspec = ShiftRotPipeSpec(id_wid=2
, parent_pspec=None
)
pspec.draft_bitmanip = True
alu = ShiftRotBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
pspec.draft_bitmanip = True
alu = ShiftRotBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
@@
-137,7
+137,7
@@
class TestRunner(unittest.TestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
pdecode = pdecode2.dec
m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
pdecode = pdecode2.dec
- pspec = ShiftRotPipeSpec(id_wid=2)
+ pspec = ShiftRotPipeSpec(id_wid=2
, parent_pspec=None
)
pspec.draft_bitmanip = True
m.submodules.alu = alu = ShiftRotBasePipe(pspec)
pspec.draft_bitmanip = True
m.submodules.alu = alu = ShiftRotBasePipe(pspec)
diff --git
a/src/soc/fu/spr/formal/proof_main_stage.py
b/src/soc/fu/spr/formal/proof_main_stage.py
index 5a1f6894dabe651a0f6331be9ce5dac4bc3c9f72..db9f86a84ed32947c76101e3dfa270a11685a8f5 100644
(file)
--- a/
src/soc/fu/spr/formal/proof_main_stage.py
+++ b/
src/soc/fu/spr/formal/proof_main_stage.py
@@
-48,7
+48,7
@@
class Driver(Elaboratable):
width = p.width
comb += p.eq(AnyConst(width))
width = p.width
comb += p.eq(AnyConst(width))
- pspec = SPRPipeSpec(id_wid=2)
+ pspec = SPRPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.dut = dut = SPRMainStage(pspec)
# frequently used aliases
m.submodules.dut = dut = SPRMainStage(pspec)
# frequently used aliases
diff --git
a/src/soc/fu/spr/test/test_pipe_caller.py
b/src/soc/fu/spr/test/test_pipe_caller.py
index d6aa34ea6b972ca0b68b34030f74dc0a9212ab47..894212bcb68549221fc8119fdfbc999e165e4b35 100644
(file)
--- a/
src/soc/fu/spr/test/test_pipe_caller.py
+++ b/
src/soc/fu/spr/test/test_pipe_caller.py
@@
-61,7
+61,7
@@
def set_alu_inputs(alu, dec2, sim):
class SPRIlangCase(TestAccumulatorBase):
def case_ilang(self):
class SPRIlangCase(TestAccumulatorBase):
def case_ilang(self):
- pspec = SPRPipeSpec(id_wid=2)
+ pspec = SPRPipeSpec(id_wid=2
, parent_pspec=None
)
alu = SPRBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("trap_pipeline.il", "w") as f:
alu = SPRBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("trap_pipeline.il", "w") as f:
@@
-139,7
+139,7
@@
class TestRunner(unittest.TestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- pspec = SPRPipeSpec(id_wid=2)
+ pspec = SPRPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.alu = alu = SPRBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
m.submodules.alu = alu = SPRBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
diff --git
a/src/soc/fu/trap/formal/proof_main_stage.py
b/src/soc/fu/trap/formal/proof_main_stage.py
index c00a3fbff4a199b21be6ff5a82da9e754af2c7eb..b94f7e732d255cc5aa1a063e012c9edd354a1c79 100644
(file)
--- a/
src/soc/fu/trap/formal/proof_main_stage.py
+++ b/
src/soc/fu/trap/formal/proof_main_stage.py
@@
-37,7
+37,7
@@
class Driver(Elaboratable):
comb = m.d.comb
rec = CompTrapOpSubset()
comb = m.d.comb
rec = CompTrapOpSubset()
- pspec = TrapPipeSpec(id_wid=2)
+ pspec = TrapPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.dut = dut = TrapMainStage(pspec)
m.submodules.dut = dut = TrapMainStage(pspec)
diff --git
a/src/soc/fu/trap/test/test_pipe_caller.py
b/src/soc/fu/trap/test/test_pipe_caller.py
index 5b52860a96326372a6f0f19448a8335e9e3e6c5e..428d3e72be2c1aeaa3fc525a2a8a8e3e10c70df4 100644
(file)
--- a/
src/soc/fu/trap/test/test_pipe_caller.py
+++ b/
src/soc/fu/trap/test/test_pipe_caller.py
@@
-66,7
+66,7
@@
def set_alu_inputs(alu, dec2, sim):
class TrapIlangCase(TestAccumulatorBase):
def case_ilang(self):
class TrapIlangCase(TestAccumulatorBase):
def case_ilang(self):
- pspec = TrapPipeSpec(id_wid=2)
+ pspec = TrapPipeSpec(id_wid=2
, parent_pspec=None
)
alu = TrapBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("trap_pipeline.il", "w") as f:
alu = TrapBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("trap_pipeline.il", "w") as f:
@@
-87,7
+87,7
@@
class TestRunner(unittest.TestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- pspec = TrapPipeSpec(id_wid=2)
+ pspec = TrapPipeSpec(id_wid=2
, parent_pspec=None
)
m.submodules.alu = alu = TrapBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
m.submodules.alu = alu = TrapBasePipe(pspec)
comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)