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comments and whitespace cleanup
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 4 Mar 2019 09:09:08 +0000
(09:09 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 4 Mar 2019 09:09:08 +0000
(09:09 +0000)
TLB/src/TLB.py
patch
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diff --git
a/TLB/src/TLB.py
b/TLB/src/TLB.py
index b11e49e361fb6c8d6db86a07f249f0875669ec29..dc151ce28fcca0f25a4005a4900dd67b42b7e963 100644
(file)
--- a/
TLB/src/TLB.py
+++ b/
TLB/src/TLB.py
@@
-18,21
+18,21
@@
class TLB():
self.asid = Signal(15) # Address Space IDentifier (ASID)
self.vma = Signal(36) # Virtual Memory Address (VMA)
self.pte_in = Signal(64) # To be saved Page Table Entry (PTE)
self.asid = Signal(15) # Address Space IDentifier (ASID)
self.vma = Signal(36) # Virtual Memory Address (VMA)
self.pte_in = Signal(64) # To be saved Page Table Entry (PTE)
-
+
# Outputs
self.hit = Signal(1) # Denotes if the VMA had a mapped PTE
self.valid = Signal(1) # Denotes if the permissions are correct
self.pteOut = Signal(64) # PTE that was mapped to by the VMA
# Outputs
self.hit = Signal(1) # Denotes if the VMA had a mapped PTE
self.valid = Signal(1) # Denotes if the permissions are correct
self.pteOut = Signal(64) # PTE that was mapped to by the VMA
-
+
# Cam simulations
mem_l1 = Memory(113, 32) # L1 TLB cache
read_port_l1 = mem_l1.read_port
write_port_l1 = mem_l1.write_port
# Cam simulations
mem_l1 = Memory(113, 32) # L1 TLB cache
read_port_l1 = mem_l1.read_port
write_port_l1 = mem_l1.write_port
-
+
mem_l2 = Memory(113, 128) # L2 TLB cache
read_port_l2 = mem_l2.read_port
write_port_l2 = mem_l2.write_port
mem_l2 = Memory(113, 128) # L2 TLB cache
read_port_l2 = mem_l2.read_port
write_port_l2 = mem_l2.write_port
-
+
def elaborate(self, platform):
m = Module()
m.d.submodules.perm_valid = perm_valid = PermissionValidator(113)
def elaborate(self, platform):
m = Module()
m.d.submodules.perm_valid = perm_valid = PermissionValidator(113)
@@
-60,13
+60,13
@@
class TLB():
perm_valid.super_access.eq(self.super_access),
perm_valid.asid.eq(self.asid),
self.valid,eq(perm_valid.valid)
perm_valid.super_access.eq(self.super_access),
perm_valid.asid.eq(self.asid),
self.valid,eq(perm_valid.valid)
- )
+ )
)
]
})
]
return m
)
]
})
]
return m
-
+
thing = TLB()
print("Gottem")
thing = TLB()
print("Gottem")
-
+