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sigh trying to find the right clock line
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 5 Jun 2021 17:08:44 +0000
(17:08 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 5 Jun 2021 17:08:44 +0000
(17:08 +0000)
experiments9/doDesign.py
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diff --git
a/experiments9/doDesign.py
b/experiments9/doDesign.py
index 0eba1cf492ae6809ac238a3e9cd36d339cf6b3b7..062c88d9b5f4c19e247c463235153579e0208748 100644
(file)
--- a/
experiments9/doDesign.py
+++ b/
experiments9/doDesign.py
@@
-58,8
+58,10
@@
def scriptMain (**kw):
ls180Conf.chipConf.ioPadGauge = 'niolib'
ls180Conf.coreSize = (l(coreSize ), l(coreSize ))
ls180Conf.chipSize = (l(coreSize+3360), l(coreSize+3360))
ls180Conf.chipConf.ioPadGauge = 'niolib'
ls180Conf.coreSize = (l(coreSize ), l(coreSize ))
ls180Conf.chipSize = (l(coreSize+3360), l(coreSize+3360))
- ls180Conf.useHTree('por_clk') # output from the PLL, needs to be H-Tree
+ #ls180Conf.useHTree('core.por_clk') # output from the PLL, needs to be H-Tree
+ #ls180Conf.useHTree('test_issuer.pllclk_clk') # output from the PLL, needs to be H-Tree
ls180Conf.useHTree('jtag_tck_from_pad')
ls180Conf.useHTree('jtag_tck_from_pad')
+ ls180Conf.useHTree('sys_clk_from_pad')
ls180ToChip = CoreToChip( ls180Conf )
ls180ToChip.buildChip()
ls180ToChip = CoreToChip( ls180Conf )
ls180ToChip.buildChip()