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author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 6 Apr 2021 15:07:42 +0000
(16:07 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 6 Apr 2021 15:07:42 +0000
(16:07 +0100)
ls180/pre_pnr/test.py
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diff --git
a/ls180/pre_pnr/test.py
b/ls180/pre_pnr/test.py
index b6dd38b6faf9f2f968e7ab969094c3506d57f712..9abada1afa8c8d0c60bacc2a5c4152f26fd77c32 100644
(file)
--- a/
ls180/pre_pnr/test.py
+++ b/
ls180/pre_pnr/test.py
@@
-302,8
+302,11
@@
def boundary_scan_run(dut):
@cocotb.test()
def wishbone_basic(dut):
@cocotb.test()
def wishbone_basic(dut):
- """
- Test of an added Wishbone interface
+ """Test of an added Wishbone interface
+
+ for this test the soc JTAG TAP address width is 29 bits and data is 64
+ JTAG has access to the *full* memory range, including peripherals,
+ as defined by the litex setup.
"""
clk_period = 100 # 10MHz
tck_period = 300 # 3MHz
"""
clk_period = 100 # 10MHz
tck_period = 300 # 3MHz
@@
-323,6
+326,7
@@
def wishbone_basic(dut):
yield master.load_ir(cmd_MEMADDRESS)
dut._log.info("Loading address")
yield master.load_ir(cmd_MEMADDRESS)
dut._log.info("Loading address")
+ # WBaddresses in soc.debug.jtag.JTAG are 29 bits
data_in.binstr = "00000000000000000000000000001"
dut._log.info(" input: {}".format(data_in.binstr))
yield master.shift_data(data_in)
data_in.binstr = "00000000000000000000000000001"
dut._log.info(" input: {}".format(data_in.binstr))
yield master.shift_data(data_in)
@@
-332,6
+336,7
@@
def wishbone_basic(dut):
yield master.load_ir(cmd_MEMREADWRITE)
dut._log.info("Writing memory")
yield master.load_ir(cmd_MEMREADWRITE)
dut._log.info("Writing memory")
+ # data is 64-bit
data_in.binstr = "01010101" * 8
dut._log.info(" input: {}".format(data_in.binstr))
yield master.shift_data(data_in)
data_in.binstr = "01010101" * 8
dut._log.info(" input: {}".format(data_in.binstr))
yield master.shift_data(data_in)