+ void write_sigspec(const RTLIL::SigSpec& sig, uint16_t indent_level = 0) {
+ const auto _indent = gen_indent(indent_level);
+
+ f << _indent << " {\n";
+ f << _indent << " \"width\": \"" << sig.size() << "\",\n";
+ f << _indent << " \"type\": \"";
+
+ if (sig.is_wire()) {
+ f << "wire";
+ } else if (sig.is_chunk()) {
+ f << "chunk";
+ } else if (sig.is_bit()) {
+ f << "bit";
+ } else {
+ f << "unknown";
+ }
+ f << "\",\n";
+
+ f << _indent << " \"const\": ";
+ if (sig.has_const()) {
+ f << "true";
+ } else {
+ f << "false";
+ }
+
+ f << "\n";
+
+ f << _indent << " }";
+ }
+
+ void write_mod_conn(const std::pair<RTLIL::SigSpec, RTLIL::SigSpec>& conn, uint16_t indent_level = 0) {
+ const auto _indent = gen_indent(indent_level);
+ f << _indent << " {\n";
+ f << _indent << " \"signals\": [\n";
+
+ write_sigspec(conn.first, indent_level + 2);
+ f << ",\n";
+ write_sigspec(conn.second, indent_level + 2);
+ f << "\n";
+
+ f << _indent << " ]\n";
+ f << _indent << " }";
+ }
+
+ void write_cell_conn(const std::pair<RTLIL::IdString, RTLIL::SigSpec>& sig, uint16_t indent_level = 0) {
+ const auto _indent = gen_indent(indent_level);
+ f << _indent << " {\n";
+ f << _indent << " \"name\": " << get_string(RTLIL::unescape_id(sig.first)) << ",\n";
+ f << _indent << " \"signals\": [\n";
+
+ write_sigspec(sig.second, indent_level + 2);
+ f << "\n";
+
+ f << _indent << " ]\n";
+ f << _indent << " }";
+ }
+