- def set_reset_address(self, reset_address):
- assert not hasattr(self, "reset_address")
- self.reset_address = reset_address
- assert reset_address == 0x00000000
-
- def add_sources(self, platform):
- vdir = get_data_mod("cpu", "vexriscv_smp").data_location
- print(f"VexRiscv cluster : {self.cluster_name}")
- if not path.exists(os.path.join(vdir, self.cluster_name + ".v")):
- self.generate_netlist()
-
- platform.add_source(os.path.join(vdir, "RamXilinx.v"), "verilog")
- platform.add_source(os.path.join(vdir, self.cluster_name + ".v"), "verilog")
-
- def add_memory_buses(self, address_width, data_width):
- VexRiscvSMP.litedram_width = data_width
-
- VexRiscvSMP.generate_cluster_name()