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add il generation by default
author
Jacob Lifshay
<programmerjake@gmail.com>
Tue, 1 Mar 2022 22:52:30 +0000
(14:52 -0800)
committer
Jacob Lifshay
<programmerjake@gmail.com>
Tue, 1 Mar 2022 22:52:30 +0000
(14:52 -0800)
src/nmutil/grev.py
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diff --git
a/src/nmutil/grev.py
b/src/nmutil/grev.py
index 35b45657eb5895028a88d7927454fbe2398cc27a..2b22fe1bf35ba3e5f2787b62bbf36c329a444787 100644
(file)
--- a/
src/nmutil/grev.py
+++ b/
src/nmutil/grev.py
@@
-83,6
+83,7
@@
from nmigen.hdl.ast import Signal, Mux, Cat
from nmigen.hdl.ast import Assert
from nmigen.hdl.dsl import Module
from nmigen.hdl.ir import Elaboratable
from nmigen.hdl.ast import Assert
from nmigen.hdl.dsl import Module
from nmigen.hdl.ir import Elaboratable
+from nmigen.back import rtlil
import string
import string
@@
-261,3
+262,9
@@
class GRev(Elaboratable):
# useful to see what is going on:
# python3 src/nmutil/test/test_grev.py
# yosys <<<"read_ilang sim_test_out/__main__.TestGrev.test_small/0.il; proc; clean -purge; show top"
# useful to see what is going on:
# python3 src/nmutil/test/test_grev.py
# yosys <<<"read_ilang sim_test_out/__main__.TestGrev.test_small/0.il; proc; clean -purge; show top"
+
+if __name__ == '__main__':
+ dut = GRev(3)
+ vl = rtlil.convert(dut, ports=dut.ports())
+ with open("grev3.il", "w") as f:
+ f.write(vl)