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pass in freq setting to nextpnr-xilinx
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 4 May 2022 14:11:23 +0000
(15:11 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 4 May 2022 14:11:23 +0000
(15:11 +0100)
also allow timing fail
src/ls2.py
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diff --git
a/src/ls2.py
b/src/ls2.py
index 493442b02807a3b3f9eb5833266acc0efe30039e..4ab93f9e135aef3e903a61484c924b8408ec427f 100644
(file)
--- a/
src/ls2.py
+++ b/
src/ls2.py
@@
-871,7
+871,7
@@
def build_platform(fpga, firmware):
clk_freq = 50e6
dram_clk_freq = 100e6
if fpga == 'arty_a7':
clk_freq = 50e6
dram_clk_freq = 100e6
if fpga == 'arty_a7':
- clk_freq = 2
5
.0e6 # urrr "working" with the QSPI core (25 mhz does not)
+ clk_freq = 2
7
.0e6 # urrr "working" with the QSPI core (25 mhz does not)
if fpga == 'ulx3s':
clk_freq = 40.0e6
if fpga == 'orangecrab':
if fpga == 'ulx3s':
clk_freq = 40.0e6
if fpga == 'orangecrab':
@@
-1106,7
+1106,9
@@
def build_platform(fpga, firmware):
if toolchain == 'yosys_nextpnr':
# add --seed 2 to arty a7 compile-time options
if toolchain == 'yosys_nextpnr':
# add --seed 2 to arty a7 compile-time options
- os.environ['NMIGEN_nextpnr_opts'] = '--seed 1'
+ freq = clk_freq/1e6
+ os.environ['NMIGEN_nextpnr_opts'] = '--seed 3 --freq %.1f' % freq
+ os.environ['NMIGEN_nextpnr_opts'] += ' --timing-allow-fail'
if platform is not None:
# build and upload it
if platform is not None:
# build and upload it