+(* \nmigen.hierarchy = "test_issuer.ti.sram4k_0" *)
+(* generator = "nMigen" *)
+module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, clk);
+ reg \initial = 0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *)
+ wire \$1 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
+ reg [8:0] a;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ input clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
+ reg [63:0] d;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *)
+ input enable;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
+ wire [63:0] q;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ input rst;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ output sram4k_0_wb__ack;
+ reg sram4k_0_wb__ack = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ reg \sram4k_0_wb__ack$next ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [8:0] sram4k_0_wb__adr;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_0_wb__cyc;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ output [63:0] sram4k_0_wb__dat_r;
+ reg [63:0] sram4k_0_wb__dat_r;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [63:0] sram4k_0_wb__dat_w;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [7:0] sram4k_0_wb__sel;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_0_wb__stb;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_0_wb__we;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *)
+ reg wb_active;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:45" *)
+ reg [7:0] we;
+ assign \$1 = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_0_wb__stb;
+ always @(posedge clk)
+ sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ;
+ spblock_512w64b8w \spblock_512w64b8w_%s (
+ .a(a),
+ .clk(clk),
+ .d(d),
+ .q(q),
+ .we(we)
+ );
+ always @* begin
+ if (\initial ) begin end
+ wb_active = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ wb_active = \$1 ;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \sram4k_0_wb__ack$next = sram4k_0_wb__ack;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ \sram4k_0_wb__ack$next = wb_active;
+ endcase
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (rst)
+ 1'h1:
+ \sram4k_0_wb__ack$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ a = 9'h000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ a = sram4k_0_wb__adr;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ sram4k_0_wb__dat_r = 64'h0000000000000000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ sram4k_0_wb__dat_r = q;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ d = 64'h0000000000000000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ d = sram4k_0_wb__dat_w;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ we = 8'h00;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" *)
+ casez (sram4k_0_wb__we)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" */
+ 1'h1:
+ we = sram4k_0_wb__sel;
+ endcase
+ endcase
+ endcase
+ end
+endmodule
+
+(* \nmigen.hierarchy = "test_issuer.ti.sram4k_1" *)
+(* generator = "nMigen" *)
+module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, clk);
+ reg \initial = 0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *)
+ wire \$1 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
+ reg [8:0] a;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ input clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
+ reg [63:0] d;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *)
+ input enable;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
+ wire [63:0] q;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ input rst;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ output sram4k_1_wb__ack;
+ reg sram4k_1_wb__ack = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ reg \sram4k_1_wb__ack$next ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [8:0] sram4k_1_wb__adr;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_1_wb__cyc;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ output [63:0] sram4k_1_wb__dat_r;
+ reg [63:0] sram4k_1_wb__dat_r;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [63:0] sram4k_1_wb__dat_w;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [7:0] sram4k_1_wb__sel;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_1_wb__stb;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_1_wb__we;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *)
+ reg wb_active;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:45" *)
+ reg [7:0] we;
+ assign \$1 = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_1_wb__stb;
+ always @(posedge clk)
+ sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ;
+ spblock_512w64b8w \spblock_512w64b8w_%s (
+ .a(a),
+ .clk(clk),
+ .d(d),
+ .q(q),
+ .we(we)
+ );
+ always @* begin
+ if (\initial ) begin end
+ wb_active = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ wb_active = \$1 ;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \sram4k_1_wb__ack$next = sram4k_1_wb__ack;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ \sram4k_1_wb__ack$next = wb_active;
+ endcase
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (rst)
+ 1'h1:
+ \sram4k_1_wb__ack$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ a = 9'h000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ a = sram4k_1_wb__adr;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ sram4k_1_wb__dat_r = 64'h0000000000000000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ sram4k_1_wb__dat_r = q;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ d = 64'h0000000000000000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ d = sram4k_1_wb__dat_w;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ we = 8'h00;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" *)
+ casez (sram4k_1_wb__we)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" */
+ 1'h1:
+ we = sram4k_1_wb__sel;
+ endcase
+ endcase
+ endcase
+ end
+endmodule
+
+(* \nmigen.hierarchy = "test_issuer.ti.sram4k_2" *)
+(* generator = "nMigen" *)
+module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, clk);
+ reg \initial = 0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *)
+ wire \$1 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
+ reg [8:0] a;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ input clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
+ reg [63:0] d;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *)
+ input enable;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
+ wire [63:0] q;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ input rst;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ output sram4k_2_wb__ack;
+ reg sram4k_2_wb__ack = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ reg \sram4k_2_wb__ack$next ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [8:0] sram4k_2_wb__adr;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_2_wb__cyc;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ output [63:0] sram4k_2_wb__dat_r;
+ reg [63:0] sram4k_2_wb__dat_r;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [63:0] sram4k_2_wb__dat_w;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [7:0] sram4k_2_wb__sel;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_2_wb__stb;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_2_wb__we;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *)
+ reg wb_active;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:45" *)
+ reg [7:0] we;
+ assign \$1 = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_2_wb__stb;
+ always @(posedge clk)
+ sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ;
+ spblock_512w64b8w \spblock_512w64b8w_%s (
+ .a(a),
+ .clk(clk),
+ .d(d),
+ .q(q),
+ .we(we)
+ );
+ always @* begin
+ if (\initial ) begin end
+ wb_active = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ wb_active = \$1 ;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \sram4k_2_wb__ack$next = sram4k_2_wb__ack;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ \sram4k_2_wb__ack$next = wb_active;
+ endcase
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (rst)
+ 1'h1:
+ \sram4k_2_wb__ack$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ a = 9'h000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ a = sram4k_2_wb__adr;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ sram4k_2_wb__dat_r = 64'h0000000000000000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ sram4k_2_wb__dat_r = q;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ d = 64'h0000000000000000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ d = sram4k_2_wb__dat_w;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ we = 8'h00;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" *)
+ casez (sram4k_2_wb__we)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" */
+ 1'h1:
+ we = sram4k_2_wb__sel;
+ endcase
+ endcase
+ endcase
+ end
+endmodule
+
+(* \nmigen.hierarchy = "test_issuer.ti.sram4k_3" *)
+(* generator = "nMigen" *)
+module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, clk);
+ reg \initial = 0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *)
+ wire \$1 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
+ reg [8:0] a;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ input clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
+ reg [63:0] d;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *)
+ input enable;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
+ wire [63:0] q;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ input rst;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ output sram4k_3_wb__ack;
+ reg sram4k_3_wb__ack = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ reg \sram4k_3_wb__ack$next ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [8:0] sram4k_3_wb__adr;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_3_wb__cyc;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ output [63:0] sram4k_3_wb__dat_r;
+ reg [63:0] sram4k_3_wb__dat_r;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [63:0] sram4k_3_wb__dat_w;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input [7:0] sram4k_3_wb__sel;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_3_wb__stb;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
+ input sram4k_3_wb__we;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *)
+ reg wb_active;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:45" *)
+ reg [7:0] we;
+ assign \$1 = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_3_wb__stb;
+ always @(posedge clk)
+ sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ;
+ spblock_512w64b8w \spblock_512w64b8w_%s (
+ .a(a),
+ .clk(clk),
+ .d(d),
+ .q(q),
+ .we(we)
+ );
+ always @* begin
+ if (\initial ) begin end
+ wb_active = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ wb_active = \$1 ;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \sram4k_3_wb__ack$next = sram4k_3_wb__ack;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ \sram4k_3_wb__ack$next = wb_active;
+ endcase
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (rst)
+ 1'h1:
+ \sram4k_3_wb__ack$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ a = 9'h000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ a = sram4k_3_wb__adr;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ sram4k_3_wb__dat_r = 64'h0000000000000000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ sram4k_3_wb__dat_r = q;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ d = 64'h0000000000000000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ d = sram4k_3_wb__dat_w;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ we = 8'h00;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *)
+ casez (enable)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *)
+ casez (wb_active)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */
+ 1'h1:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" *)
+ casez (sram4k_3_wb__we)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" */
+ 1'h1:
+ we = sram4k_3_wb__sel;
+ endcase
+ endcase
+ endcase
+ end
+endmodule
+