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examples/sdram_soc: reduce L1 sizes to 1KB to meet timing.
author
Jean-François Nguyen
<jf@lambdaconcept.com>
Thu, 1 Jul 2021 13:49:17 +0000
(15:49 +0200)
committer
Jean-François Nguyen
<jf@lambdaconcept.com>
Thu, 1 Jul 2021 13:49:17 +0000
(15:49 +0200)
examples/sdram_soc.py
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diff --git
a/examples/sdram_soc.py
b/examples/sdram_soc.py
index bbe68ebc6a5a89c20cfdff04c052d5a03ddc2b2c..d3f5dcbced5642fc2627d2aa010719ec419ba6c0 100644
(file)
--- a/
examples/sdram_soc.py
+++ b/
examples/sdram_soc.py
@@
-32,9
+32,9
@@
class SDRAMSoC(CPUSoC, Elaboratable):
self.cpu = MinervaCPU(
reset_address=reset_addr,
self.cpu = MinervaCPU(
reset_address=reset_addr,
- with_icache=True, icache_nlines=
128
, icache_nwords=4, icache_nways=1,
+ with_icache=True, icache_nlines=
64
, icache_nwords=4, icache_nways=1,
icache_base=sdram_addr, icache_limit=sdram_addr + sdram_core.size,
icache_base=sdram_addr, icache_limit=sdram_addr + sdram_core.size,
- with_dcache=True, dcache_nlines=
128
, dcache_nwords=4, dcache_nways=1,
+ with_dcache=True, dcache_nlines=
64
, dcache_nwords=4, dcache_nways=1,
dcache_base=sdram_addr, dcache_limit=sdram_addr + sdram_core.size,
with_muldiv=True,
)
dcache_base=sdram_addr, dcache_limit=sdram_addr + sdram_core.size,
with_muldiv=True,
)