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Update unit test to pass. Needs more testing for multiple match.
author
Daniel Benusovich
<flyingmonkeys1996@gmail.com>
Tue, 5 Mar 2019 08:51:10 +0000
(
00:51
-0800)
committer
Daniel Benusovich
<flyingmonkeys1996@gmail.com>
Tue, 5 Mar 2019 08:51:10 +0000
(
00:51
-0800)
TLB/test/test_cam.py
patch
|
blob
|
history
diff --git
a/TLB/test/test_cam.py
b/TLB/test/test_cam.py
index 18dbfbbfd0519a817d6dc04b2fe983e69c203744..00474feb9ff17c8e51151826d296cd82370d0fec 100644
(file)
--- a/
TLB/test/test_cam.py
+++ b/
TLB/test/test_cam.py
@@
-15,23
+15,23
@@
def set_cam(dut, e, we, a, d):
yield dut.data_in.eq(d)
yield
yield dut.data_in.eq(d)
yield
-def check_
data_hit
(dut, dh, op):
- out_
dh
= yield dut.single_match
+def check_
single_match
(dut, dh, op):
+ out_
sm
= yield dut.single_match
if op == 0:
if op == 0:
- assert_eq("
Data Hit", out_dh
, dh)
+ assert_eq("
Single Match", out_sm
, dh)
else:
else:
- assert_ne("
Data Hit", out_dh
, dh)
+ assert_ne("
Single Match", out_sm
, dh)
-def check_
data(dut, d
, op):
- out_
d = yield dut.data_out
+def check_
match_address(dut, ma
, op):
+ out_
ma = yield dut.match_address
if op == 0:
if op == 0:
- assert_eq("
Data", out_d, d
)
+ assert_eq("
Match Address", out_ma, ma
)
else:
else:
- assert_ne("
Data", out_d, d
)
+ assert_ne("
Match Address", out_ma, ma
)
-def check_all(dut,
data_hit, data, dh_op, d
_op):
- yield from check_
data_hit(dut, data_hit, dh
_op)
- yield from check_
data(dut, data, d
_op)
+def check_all(dut,
single_match, match_address, sm_op, ma
_op):
+ yield from check_
single_match(dut, single_match, sm
_op)
+ yield from check_
match_address(dut, match_address, ma
_op)
def testbench(dut):
def testbench(dut):
@@
-40,60
+40,60
@@
def testbench(dut):
write_enable = 0
address = 0
data = 0
write_enable = 0
address = 0
data = 0
-
data_hit
= 0
+
single_match
= 0
yield from set_cam(dut, enable, write_enable, address, data)
yield from set_cam(dut, enable, write_enable, address, data)
- yield from check_
data_hit(dut, data_hit
, 0)
+ yield from check_
single_match(dut, single_match
, 0)
- #
Search
Miss
+ #
Read
Miss
# Note that the default starting entry data bits are all 0
enable = 1
write_enable = 0
address = 0
data = 1
# Note that the default starting entry data bits are all 0
enable = 1
write_enable = 0
address = 0
data = 1
-
data_hit
= 0
+
single_match
= 0
yield from set_cam(dut, enable, write_enable, address, data)
yield
yield from set_cam(dut, enable, write_enable, address, data)
yield
- yield from check_
data_hit(dut, data_hit
, 0)
+ yield from check_
single_match(dut, single_match
, 0)
# Write Entry 0
enable = 1
write_enable = 1
address = 0
data = 4
# Write Entry 0
enable = 1
write_enable = 1
address = 0
data = 4
-
data_hit
= 0
+
single_match
= 0
yield from set_cam(dut, enable, write_enable, address, data)
yield
yield from set_cam(dut, enable, write_enable, address, data)
yield
- yield from check_
data_hit(dut, data_hit
, 0)
+ yield from check_
single_match(dut, single_match
, 0)
- # Read Entry 0
+ # Read
Hit
Entry 0
enable = 1
write_enable = 0
address = 0
data = 4
enable = 1
write_enable = 0
address = 0
data = 4
-
data_hit
= 1
+
single_match
= 1
yield from set_cam(dut, enable, write_enable, address, data)
yield
yield from set_cam(dut, enable, write_enable, address, data)
yield
-
#yield from check_all(dut, data_hit, data
, 0, 0)
+
yield from check_all(dut, single_match, address
, 0, 0)
# Search Hit
enable = 1
write_enable = 0
address = 0
data = 4
# Search Hit
enable = 1
write_enable = 0
address = 0
data = 4
-
data_hit
= 1
+
single_match
= 1
yield from set_cam(dut, enable, write_enable, address, data)
yield
yield from set_cam(dut, enable, write_enable, address, data)
yield
-
#yield from check_all(dut, data_hit, data
, 0, 0)
+
yield from check_all(dut, single_match, address
, 0, 0)
# Search Miss
enable = 1
write_enable = 0
address = 0
data = 5
# Search Miss
enable = 1
write_enable = 0
address = 0
data = 5
-
data_hit
= 0
+
single_match
= 0
yield from set_cam(dut, enable, write_enable, address, data)
yield
yield from set_cam(dut, enable, write_enable, address, data)
yield
- #yield from check_all(dut, data_hit, data, 0, 1)
+ yield from check_single_match(dut, single_match, 0)
yield
yield