+ has_tercel : if USE_TERCEL generate
+
+ component tercel_core port (
+ sys_clk_freq : in std_ulogic_vector(31 downto 0);
+
+ peripheral_clock : in std_ulogic;
+ peripheral_reset : in std_ulogic;
+
+ spi_clock : out std_ulogic;
+ spi_d_out : out std_ulogic_vector(3 downto 0);
+ spi_d_direction : out std_ulogic_vector(3 downto 0);
+ spi_d_in : in std_ulogic_vector(3 downto 0);
+ spi_ss_n : out std_ulogic;
+
+ wishbone_adr : in std_ulogic_vector(29 downto 0);
+ wishbone_dat_w : in std_ulogic_vector(31 downto 0);
+ wishbone_dat_r : out std_ulogic_vector(31 downto 0);
+ wishbone_sel : in std_ulogic_vector(3 downto 0);
+ wishbone_cyc : in std_ulogic;
+ wishbone_stb : in std_ulogic;
+ wishbone_ack : out std_ulogic;
+ wishbone_we : in std_ulogic;
+ wishbone_err : out std_ulogic;
+
+ cfg_wishbone_adr : in std_ulogic_vector(29 downto 0);
+ cfg_wishbone_dat_w : in std_ulogic_vector(31 downto 0);
+ cfg_wishbone_dat_r : out std_ulogic_vector(31 downto 0);
+ cfg_wishbone_sel : in std_ulogic_vector(3 downto 0);
+ cfg_wishbone_cyc : in std_ulogic;
+ cfg_wishbone_stb : in std_ulogic;
+ cfg_wishbone_ack : out std_ulogic;
+ cfg_wishbone_we : in std_ulogic;
+ cfg_wishbone_err : out std_ulogic
+ );
+ end component;
+
+ signal wb_tercel_cyc : std_ulogic;
+
+ begin
+ tercel : tercel_core
+ port map(
+ sys_clk_freq => std_logic_vector(to_unsigned(CLK_FREQUENCY, 32)),
+
+ peripheral_clock => system_clk,
+ peripheral_reset => soc_rst,
+
+ spi_clock => spi_sck,
+ spi_d_out => spi_sdat_o,
+ spi_d_direction => spi_sdat_oe,
+ spi_d_in => spi_sdat_i,
+ spi_ss_n => spi_cs_n,
+
+ wishbone_adr => wb_spiflash_in.adr,
+ wishbone_dat_w => wb_spiflash_in.dat,
+ wishbone_dat_r => wb_spiflash_out.dat,
+ wishbone_sel => wb_spiflash_in.sel,
+ wishbone_cyc => wb_spiflash_in.cyc,
+ wishbone_stb => wb_spiflash_in.stb,
+ wishbone_ack => wb_spiflash_out.ack,
+ wishbone_we => wb_spiflash_in.we,
+ wishbone_err => open,
+
+ cfg_wishbone_adr => wb_ext_io_in.adr,
+ cfg_wishbone_dat_w => wb_ext_io_in.dat,
+ cfg_wishbone_dat_r => wb_tercel_out.dat,
+ cfg_wishbone_sel => wb_ext_io_in.sel,
+ cfg_wishbone_cyc => wb_tercel_cyc,
+ cfg_wishbone_stb => wb_ext_io_in.stb,
+ cfg_wishbone_ack => wb_tercel_out.ack,
+ cfg_wishbone_we => wb_ext_io_in.we,
+ cfg_wishbone_err => open
+ );
+
+ -- Gate cyc with "chip select" from soc
+ wb_tercel_cyc <= wb_ext_io_in.cyc and wb_ext_is_tercel;
+
+ -- Tercel isn't pipelined
+ wb_tercel_out.stall <= not wb_tercel_out.ack;
+
+ end generate;
+