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Fix commit 8313d6e7.
author
whitequark
<whitequark@whitequark.org>
Fri, 6 Nov 2020 01:54:25 +0000
(
01:54
+0000)
committer
whitequark
<whitequark@whitequark.org>
Fri, 6 Nov 2020 01:54:30 +0000
(
01:54
+0000)
nmigen/cli.py
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diff --git
a/nmigen/cli.py
b/nmigen/cli.py
index 7d5ed895a8842c7a52365501f6915d9fb25c9abe..51e9a953eb285625a3aa35a9b6257ad2c5cef419 100644
(file)
--- a/
nmigen/cli.py
+++ b/
nmigen/cli.py
@@
-2,7
+2,7
@@
import argparse
from .hdl.ir import Fragment
from .back import rtlil, cxxrtl, verilog
from .hdl.ir import Fragment
from .back import rtlil, cxxrtl, verilog
-from .sim import
pysim
+from .sim import
Simulator
__all__ = ["main"]
__all__ = ["main"]
@@
-67,7
+67,7
@@
def main_runner(parser, args, design, platform=None, name="top", ports=()):
if args.action == "simulate":
fragment = Fragment.get(design, platform)
if args.action == "simulate":
fragment = Fragment.get(design, platform)
- sim =
pysim.
Simulator(fragment)
+ sim = Simulator(fragment)
sim.add_clock(args.sync_period)
with sim.write_vcd(vcd_file=args.vcd_file, gtkw_file=args.gtkw_file, traces=ports):
sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)
sim.add_clock(args.sync_period)
with sim.write_vcd(vcd_file=args.vcd_file, gtkw_file=args.gtkw_file, traces=ports):
sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)