add more code

diff --git a/nmigen/back/pysim.pyi b/nmigen/back/pysim.pyi
index e797b5fe632495bd4b2832c00115a9869229f04f..b0254ea665c37ab0eadfc98061545c36d56b27c2 100644 (file)
--- a/nmigen/back/pysim.pyi
+++ b/nmigen/back/pysim.pyi
@@ -1,8 +1,8 @@
-from ..hdl.ast import (Signal, Statement, Delay as Delay,
+from ..hdl.ast import (Signal, Delay as Delay,

                        Tick as Tick, Passive as Passive, Assign, Value)
 from typing import Any, Iterable, Generator, Union, Callable, Optional
 
                        Tick as Tick, Passive as Passive, Assign, Value)
 from typing import Any, Iterable, Generator, Union, Callable, Optional
 

-__all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]
+__all__ = ["Simulator", "Delay", "Tick", "Passive"]

 
 ProcessCommand = Union[Delay, Tick, Passive, Assign, Value]
 ProcessGenerator = Generator[ProcessCommand, Union[int, None], None]
 
 ProcessCommand = Union[Delay, Tick, Passive, Assign, Value]
 ProcessGenerator = Generator[ProcessCommand, Union[int, None], None]

diff --git a/nmigen/cli.py b/nmigen/cli.py
deleted file mode 100644 (file)
index 9ade1c7..0000000
--- a/nmigen/cli.py
+++ /dev/null
@@ -1,5 +0,0 @@
-from typing import Any
-
-
-def main(*args: Any, **kwargs: Any) -> None:
-    ...

diff --git a/nmigen/cli.pyi b/nmigen/cli.pyi
new file mode 100644 (file)
index 0000000..9ade1c7
--- /dev/null
+++ b/nmigen/cli.pyi
@@ -0,0 +1,5 @@
+from typing import Any
+
+
+def main(*args: Any, **kwargs: Any) -> None:
+    ...

diff --git a/nmigen/hdl/ast.pyi b/nmigen/hdl/ast.pyi
index b978956cb793e02972aeedea4359b572186c246f..fbcb478d39a3aac3834a661352f8088a399887b5 100644 (file)
--- a/nmigen/hdl/ast.pyi
+++ b/nmigen/hdl/ast.pyi
@@ -1,13 +1,12 @@
 from abc import ABCMeta, abstractmethod
 from abc import ABCMeta, abstractmethod

-from typing import Union, Tuple, Any, Iterable, Optional, Mapping
+from typing import (Union, Tuple, Any, Iterable, Optional, Mapping, overload,
+                    List)

 from collections.abc import MutableSequence
 
 __all__ = [
 from collections.abc import MutableSequence
 
 __all__ = [

-    "Value", "Const", "C", "AnyConst", "AnySeq", "Operator", "Mux", "Part",
-    "Slice", "Cat", "Repl", "Array", "ArrayProxy", "Sample", "Past", "Stable",
-    "Rose", "Fell", "Signal", "ClockSignal", "ResetSignal", "Statement",
-    "Assign", "Assert", "Assume", "Switch", "Delay", "Tick", "Passive",
-    "ValueKey", "ValueDict", "ValueSet", "SignalKey", "SignalDict", "SignalSet"
+    "Value", "Const", "C", "Mux", "Cat", "Repl", "Array", "ArrayProxy",
+    "Signal", "ClockSignal", "ResetSignal", "Statement", "Assign", "Assert",
+    "Assume", "Switch", "Delay", "Tick", "Passive"

 ]
 
 ValueOrLiteral = Union[int, bool, 'Value']
 ]
 
 ValueOrLiteral = Union[int, bool, 'Value']


@@ -16,7 +15,7 @@ ShapeResult = Tuple[int, bool]
 
 class Value(metaclass=ABCMeta):
     @staticmethod
 
 class Value(metaclass=ABCMeta):
     @staticmethod

-    def wrap(obj: Any) -> 'Value':
+    def wrap(obj: ValueOrLiteral) -> 'Value':

         ...
 
     def __invert__(self) -> 'Value':
         ...
 
     def __invert__(self) -> 'Value':


@@ -112,6 +111,7 @@ class Value(metaclass=ABCMeta):
     def bool(self) -> 'Value':
         ...
 
     def bool(self) -> 'Value':
         ...
 

+    # noinspection PyMethodParameters

     def implies(premise: ValueOrLiteral,
                 conclusion: ValueOrLiteral) -> 'Value':
         ...
     def implies(premise: ValueOrLiteral,
                 conclusion: ValueOrLiteral) -> 'Value':
         ...


@@ -149,6 +149,7 @@ class Const(Value):
 C = Const
 
 
 C = Const
 
 

+# noinspection PyPep8Naming

 def Mux(sel: ValueOrLiteral,
         val1: ValueOrLiteral,
         val0: ValueOrLiteral) -> Value:
 def Mux(sel: ValueOrLiteral,
         val1: ValueOrLiteral,
         val0: ValueOrLiteral) -> Value:


@@ -175,6 +176,7 @@ class Repl(Value):
         ...
 
 
         ...
 
 

+# noinspection PyShadowingBuiltins

 class Signal(Value):
     nbits: int
     signed: bool
 class Signal(Value):
     nbits: int
     signed: bool


@@ -272,3 +274,42 @@ class Tick(Statement):
 
 class Passive(Property):
     pass
 
 class Passive(Property):
     pass

+
+
+class Array(MutableSequence):
+    def __init__(self, iterable: Iterable = ()):
+        ...
+
+    @overload
+    def __getitem__(self, index: int) -> Any:
+        ...
+
+    @overload
+    def __getitem__(self, index: Value) -> 'ArrayProxy':
+        ...
+
+    def __len__(self) -> int:
+        ...
+
+    def __setitem__(self, index: int, value: Any) -> None:
+        ...
+
+    def __delitem__(self, index: int) -> None:
+        ...
+
+    def insert(self, index: int, value: Any) -> None:
+        ...
+
+
+class ArrayProxy(Value):
+    def __init__(self, elems: Union[Array, List[Any]], index: ValueOrLiteral):
+        ...
+
+    def __getattr__(self, attr: Any) -> Any:
+        ...
+
+    def __getitem__(self, index: Any) -> Any:
+        ...
+
+    def shape(self) -> Tuple[int, bool]:
+        ...

diff --git a/nmigen/hdl/dsl.pyi b/nmigen/hdl/dsl.pyi
index cb22701cf9fba644c808c8d123ee038a1a26bb5a..2806994e62c85bec8f36b6593e405056156f99ca 100644 (file)
--- a/nmigen/hdl/dsl.pyi
+++ b/nmigen/hdl/dsl.pyi
@@ -1,6 +1,6 @@
+# noinspection PyProtectedMember

 from .ast import Statement, ValueOrLiteral, Signal
 from typing import Iterable, Union, Any, Mapping
 from .ast import Statement, ValueOrLiteral, Signal
 from typing import Iterable, Union, Any, Mapping

-from contextlib import ContextDecorator

 
 __all__ = ["Module"]
 
 
 __all__ = ["Module"]
 


@@ -50,6 +50,7 @@ class FSM:
         ...
 
 
         ...
 
 

+# noinspection PyPep8Naming

 class Module(_ModuleBuilderRoot):
     submodules: Any
 
 class Module(_ModuleBuilderRoot):
     submodules: Any
 

diff --git a/nmigen/hdl/ir.pyi b/nmigen/hdl/ir.pyi
index b62b8f296d2df8fa579497a7f54685ee70f58345..6ae482f7a96856fe0b7576c54d304ee616439183 100644 (file)
--- a/nmigen/hdl/ir.pyi
+++ b/nmigen/hdl/ir.pyi
@@ -1,6 +1,7 @@
-from typing import Optional, Generator, Any, Tuple, Iterable, Union, List
+from typing import Optional, Generator, Any, Tuple, Iterable, Union

 from .ast import Signal, Statement
 from .cd import ClockDomain
 from .ast import Signal, Statement
 from .cd import ClockDomain

+# noinspection PyProtectedMember

 from .dsl import FSM
 
 __all__ = ["Fragment", "Instance", "DriverConflict"]
 from .dsl import FSM
 
 __all__ = ["Fragment", "Instance", "DriverConflict"]


@@ -10,6 +11,7 @@ class DriverConflict(UserWarning):
     pass
 
 
     pass
 
 

+# noinspection PyShadowingBuiltins

 class Fragment:
     @staticmethod
     def get(obj: Any, platform: Any) -> 'Fragment':
 class Fragment:
     @staticmethod
     def get(obj: Any, platform: Any) -> 'Fragment':


@@ -73,5 +75,6 @@ class Fragment:
 
 
 class Instance(Fragment):
 
 
 class Instance(Fragment):

+    # noinspection PyShadowingBuiltins

     def __init__(self, type: str, **kwargs: Any):
         ...
     def __init__(self, type: str, **kwargs: Any):
         ...

diff --git a/nmigen/hdl/mem.pyi b/nmigen/hdl/mem.pyi
index 8ebdff09706f232d211ff9d66ece63ffc0e44054..4dc8caf07f6ea33eeaedbd0d80e5b892a4ae055e 100644 (file)
--- a/nmigen/hdl/mem.pyi
+++ b/nmigen/hdl/mem.pyi
@@ -1,7 +1,7 @@
 from typing import Optional, Iterable, List, Union
 from .ast import Signal, Const
 
 from typing import Optional, Iterable, List, Union
 from .ast import Signal, Const
 

-__all__ = ["Memory", "ReadPort", "WritePort", "DummyPort"]
+__all__ = ["Memory", "ReadPort", "WritePort"]

 
 
 class ReadPort:
 
 
 class ReadPort:


@@ -37,6 +37,7 @@ class Memory:
                  simulate: bool = True):
         ...
 
                  simulate: bool = True):
         ...
 

+    # noinspection PyPropertyDefinition

     @property
     def init(self) -> List[int]:
         ...
     @property
     def init(self) -> List[int]:
         ...

diff --git a/nmigen/tools.py b/nmigen/tools.py
deleted file mode 100644 (file)
index d5be0db..0000000
--- a/nmigen/tools.py
+++ /dev/null
@@ -1,6 +0,0 @@
-def log2_int(n: int, need_pow2: bool = True) -> int:
-    ...
-
-
-def bits_for(n: int, require_sign_bit: bool = False) -> int:
-    ...

diff --git a/nmigen/tools.pyi b/nmigen/tools.pyi
new file mode 100644 (file)
index 0000000..d5be0db
--- /dev/null
+++ b/nmigen/tools.pyi
@@ -0,0 +1,6 @@
+def log2_int(n: int, need_pow2: bool = True) -> int:
+    ...
+
+
+def bits_for(n: int, require_sign_bit: bool = False) -> int:
+    ...