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Reorganizing signal sizes within inputs
author
Daniel Benusovich
<flyingmonkeys1996@gmail.com>
Sat, 16 Feb 2019 21:26:12 +0000
(13:26 -0800)
committer
Daniel Benusovich
<flyingmonkeys1996@gmail.com>
Sat, 16 Feb 2019 21:26:12 +0000
(13:26 -0800)
TLB/TLB.py
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diff --git
a/TLB/TLB.py
b/TLB/TLB.py
index adbf291f47c74f10c2ffe7ac9749fa06233ea5df..b11e49e361fb6c8d6db86a07f249f0875669ec29 100644
(file)
--- a/
TLB/TLB.py
+++ b/
TLB/TLB.py
@@
-1,5
+1,6
@@
from nmigen import Memory, Module, Signal
from nmigen.cli import main
from nmigen import Memory, Module, Signal
from nmigen.cli import main
+
from PermissionValidator import PermissionValidator
# The expected form of the data is
from PermissionValidator import PermissionValidator
# The expected form of the data is
@@
-9,10
+10,10
@@
from PermissionValidator import PermissionValidator
class TLB():
def __init__(self):
# Inputs
class TLB():
def __init__(self):
# Inputs
- self.xwr = Signal(3) # Execute, Write, Read
self.super = Signal(1) # Supervisor Mode
self.super_access = Signal(1) # Supervisor Access
self.command = Signal(2) # 00=None, 01=Search, 10=Write PTE, 11=Reset
self.super = Signal(1) # Supervisor Mode
self.super_access = Signal(1) # Supervisor Access
self.command = Signal(2) # 00=None, 01=Search, 10=Write PTE, 11=Reset
+ self.xwr = Signal(3) # Execute, Write, Read
self.mode = Signal(4) # 4 bits for access to Sv48 on Rv64
self.asid = Signal(15) # Address Space IDentifier (ASID)
self.vma = Signal(36) # Virtual Memory Address (VMA)
self.mode = Signal(4) # 4 bits for access to Sv48 on Rv64
self.asid = Signal(15) # Address Space IDentifier (ASID)
self.vma = Signal(36) # Virtual Memory Address (VMA)
@@
-64,6
+65,8
@@
class TLB():
]
})
]
]
})
]
+ return m
thing = TLB()
print("Gottem")
thing = TLB()
print("Gottem")
+