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note update date on RFC ls004 (v2)
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 7 Feb 2024 20:16:08 +0000
(20:16 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 7 Feb 2024 20:16:08 +0000
(20:16 +0000)
openpower/sv/rfc/ls004.mdwn
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diff --git
a/openpower/sv/rfc/ls004.mdwn
b/openpower/sv/rfc/ls004.mdwn
index cdb114e466a9bd5d591fa0946ac525e6f3570b64..4fcf6577cac4616f8865d976f123de5cc093acf1 100644
(file)
--- a/
openpower/sv/rfc/ls004.mdwn
+++ b/
openpower/sv/rfc/ls004.mdwn
@@
-1,4
+1,4
@@
-# RFC ls004
Shift-And-Ad
d
+# RFC ls004
v2 Shift-And-Add and LD/ST-Shifte
d
* Funded by NLnet under the Privacy and Enhanced Trust Programme, EU
Horizon2020 Grant 825310, and NGI0 Entrust No 101069594
* Funded by NLnet under the Privacy and Enhanced Trust Programme, EU
Horizon2020 Grant 825310, and NGI0 Entrust No 101069594
@@
-16,7
+16,7
@@
**Status**: New
**Status**: New
-**Date**:
31 Oct 2022
+**Date**:
07 Feb 2024
**Target**: v3.2B
**Target**: v3.2B
@@
-39,7
+39,7
@@
sadd - Shift and Add
saddw - Shift and Add Signed Word
sadduw - Shift and Add Unsigned Word
sadd - Shift and Add
saddw - Shift and Add Signed Word
sadduw - Shift and Add Unsigned Word
- Also
under consideration LD/ST-Indexed-Shifted
+ Also
LD/ST-Indexed-Shifted (Fixed and Floating)
```
**Submitter**: Luke Leighton (Libre-SOC)
```
**Submitter**: Luke Leighton (Libre-SOC)
@@
-70,6
+70,7
@@
Power ISA is missing LD/ST Indexed with shift, which is present in both ARM
and x86. Adding more LD/ST is thirty eight instructions, a compromise is to
add shift-and-add. Replaces a pair of explicit instructions in hot-loops.
Power ISA is missing LD/ST Indexed with shift, which is present in both ARM
and x86. Adding more LD/ST is thirty eight instructions, a compromise is to
add shift-and-add. Replaces a pair of explicit instructions in hot-loops.
+Adding actual LD/ST Shifted saves even further.
**Notes and Observations**:
**Notes and Observations**: